Simulation Results: sysrst_ctrl

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.79 %
  • code
  • 91.64 %
  • assert
  • 92.05 %
  • func
  • 67.68 %
  • line
  • 96.46 %
  • branch
  • 96.92 %
  • cond
  • 93.90 %
  • toggle
  • 99.77 %
  • FSM
  • 71.15 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 3.900s 2107.449us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.730s 2482.495us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.480s 2173.873us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.240s 2311.625us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.440s 6089.832us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.630s 2042.358us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 13.680s 39460.946us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 5.740s 2587.312us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.830s 2084.318us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.630s 2042.358us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.740s 2587.312us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 20.800s 25404.137us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 71.070s 164443.431us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.420s 3002.156us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 2.000s 4512.819us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.560s 2547.217us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.280s 2271.477us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 3.020s 3662.991us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.190s 2639.264us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 6.270s 9998.908us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 37.760s 41373.425us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 4.250s 9517.242us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.960s 2043.372us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 3.770s 2015.908us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.130s 2038.318us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.130s 2038.318us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.440s 6089.832us 1 1 100.00
sysrst_ctrl_csr_rw 2.630s 2042.358us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.740s 2587.312us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 21.220s 9820.796us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.440s 6089.832us 1 1 100.00
sysrst_ctrl_csr_rw 2.630s 2042.358us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.740s 2587.312us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 21.220s 9820.796us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 9.590s 22071.971us 1 1 100.00
sysrst_ctrl_tl_intg_err 10.420s 22467.195us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 10.420s 22467.195us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 3.470s 7306.256us 1 1 100.00