Simulation Results: uart

 
29/06/2026 15:30:28 DVSim: v1.49.11 sha: 36037e5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.94 %
  • code
  • 95.93 %
  • assert
  • 98.56 %
  • func
  • 57.33 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.57 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 18.050s 6055.501us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.680s 21.632us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.670s 13.988us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.060s 1027.411us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.750s 252.486us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.110s 42.786us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.670s 13.988us 1 1 100.00
uart_csr_aliasing 0.750s 252.486us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 7.480s 16745.844us 1 1 100.00
parity 2 2 100.00
uart_smoke 18.050s 6055.501us 1 1 100.00
uart_tx_rx 7.480s 16745.844us 1 1 100.00
parity_error 2 2 100.00
uart_intr 10.870s 25562.194us 1 1 100.00
uart_rx_parity_err 14.330s 42201.986us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 7.480s 16745.844us 1 1 100.00
uart_intr 10.870s 25562.194us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 70.350s 119187.135us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 12.180s 8105.563us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 13.400s 32844.202us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 10.870s 25562.194us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 10.870s 25562.194us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 10.870s 25562.194us 1 1 100.00
perf 1 1 100.00
uart_perf 189.180s 14702.441us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.310s 1171.827us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.310s 1171.827us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 4.060s 4748.161us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 1.970s 2628.377us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.070s 540.099us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 15.820s 6280.195us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 191.660s 97398.117us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 373.800s 246279.354us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.550s 32.545us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.660s 37.387us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.350s 69.725us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.350s 69.725us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.680s 21.632us 1 1 100.00
uart_csr_rw 0.670s 13.988us 1 1 100.00
uart_csr_aliasing 0.750s 252.486us 1 1 100.00
uart_same_csr_outstanding 0.890s 20.982us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.680s 21.632us 1 1 100.00
uart_csr_rw 0.670s 13.988us 1 1 100.00
uart_csr_aliasing 0.750s 252.486us 1 1 100.00
uart_same_csr_outstanding 0.890s 20.982us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.760s 49.234us 1 1 100.00
uart_tl_intg_err 1.050s 568.452us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.050s 568.452us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 29.800s 8096.319us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 77295246836121870919603166623231249271927856207401248936978265045133973632287 76
UVM_ERROR @ 3533743836 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 3533801976 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 251 [0xfb]) reg name: uart_reg_block.rdata
UVM_ERROR @ 3620349180 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 3620372436 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty