Simulation Results: adc_ctrl

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.16 %
  • code
  • 93.17 %
  • assert
  • 92.54 %
  • func
  • 12.77 %
  • line
  • 98.86 %
  • branch
  • 97.40 %
  • cond
  • 87.22 %
  • toggle
  • 98.58 %
  • FSM
  • 83.78 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 2.430s 5926.183us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 0.890s 825.974us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.200s 577.246us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 41.190s 26511.678us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 3.130s 1072.593us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.400s 436.696us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.200s 577.246us 1 1 100.00
adc_ctrl_csr_aliasing 3.130s 1072.593us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.680s 423.927us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.860s 498.479us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.970s 417.072us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.710s 333.114us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.910s 288.227us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 1.200s 491.755us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 1.050s 330.612us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.140s 360.593us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 6.690s 4273.071us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 14.410s 42167.087us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 61.130s 79319.561us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 3.250s 7071.606us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.950s 473.251us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.760s 487.712us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.180s 744.093us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.180s 744.093us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.890s 825.974us 1 1 100.00
adc_ctrl_csr_rw 1.200s 577.246us 1 1 100.00
adc_ctrl_csr_aliasing 3.130s 1072.593us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.590s 3919.882us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.890s 825.974us 1 1 100.00
adc_ctrl_csr_rw 1.200s 577.246us 1 1 100.00
adc_ctrl_csr_aliasing 3.130s 1072.593us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.590s 3919.882us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 1.910s 3894.452us 1 1 100.00
adc_ctrl_tl_intg_err 7.100s 4196.660us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 7.100s 4196.660us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 2.010s 2111.984us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 69494533769976611038083675453512192457603831477673865312079392382688010442721 386
UVM_INFO @ 423926827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 94122917814784196054613064134173548906647158118615069437693815211374969238664 386
UVM_INFO @ 498478866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 103861651284720427798633055274145561926824861652380593505732086099975036043545 386
UVM_INFO @ 417072481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 43739998847093891057535618334672130246745863948717646289531546350629153526699 386
UVM_INFO @ 333113617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 48124872984750884079896874635465833714052157435106853426205183159723461327038 386
UVM_INFO @ 288227285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 96432283401318295042235200641088963879909323802532179551479559077639063459400 386
UVM_INFO @ 491754836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 102718090909635419607482412807355836257420715370373730605127265554775842580223 386
UVM_INFO @ 360592651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 114161826390768125278383566979483336784096261826672556609753748557900152629145 386
UVM_INFO @ 330611795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 69570789491770524379680062704007450879034576937393309120019142627140609297398 426
UVM_INFO @ 2111984433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 78328907890280515629921564693280729444030867545455269835819481370174348672884 402
UVM_INFO @ 7071605628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---