Simulation Results: aes/unmasked

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.51 %
  • code
  • 89.66 %
  • assert
  • 97.73 %
  • func
  • 75.14 %
  • block
  • 89.54 %
  • line
  • 91.74 %
  • branch
  • 80.02 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 88.857us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 81.262us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 123.414us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 106.491us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 209.870us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 95.003us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 93.488us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 106.491us 1 1 100.00
aes_csr_aliasing 2.000s 95.003us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 81.262us 1 1 100.00
aes_config_error 3.000s 133.084us 1 1 100.00
aes_stress 3.000s 64.251us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 81.262us 1 1 100.00
aes_config_error 3.000s 133.084us 1 1 100.00
aes_stress 3.000s 64.251us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 64.251us 1 1 100.00
aes_b2b 3.000s 95.529us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 64.251us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 81.262us 1 1 100.00
aes_config_error 3.000s 133.084us 1 1 100.00
aes_stress 3.000s 64.251us 1 1 100.00
aes_alert_reset 3.000s 483.398us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 57.489us 1 1 100.00
aes_config_error 3.000s 133.084us 1 1 100.00
aes_alert_reset 3.000s 483.398us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 209.880us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 847.836us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 483.398us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 64.251us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 64.251us 1 1 100.00
aes_sideload 2.000s 84.451us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 1.000s 115.714us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 14.000s 1729.424us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 67.438us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 66.697us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 66.697us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 123.414us 1 1 100.00
aes_csr_rw 2.000s 106.491us 1 1 100.00
aes_csr_aliasing 2.000s 95.003us 1 1 100.00
aes_same_csr_outstanding 2.000s 61.871us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 123.414us 1 1 100.00
aes_csr_rw 2.000s 106.491us 1 1 100.00
aes_csr_aliasing 2.000s 95.003us 1 1 100.00
aes_same_csr_outstanding 2.000s 61.871us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 140.588us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 2.000s 83.273us 0 1 0.00
aes_control_fi 22.000s 10004.684us 0 1 0.00
aes_cipher_fi 2.000s 107.909us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 138.477us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 138.477us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 138.477us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 138.477us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 189.886us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 3063.185us 1 1 100.00
aes_tl_intg_err 3.000s 342.911us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 342.911us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 483.398us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 138.477us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 138.477us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 81.262us 1 1 100.00
aes_stress 3.000s 64.251us 1 1 100.00
aes_alert_reset 3.000s 483.398us 1 1 100.00
aes_core_fi 2.000s 162.741us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 133.084us 1 1 100.00
aes_stress 3.000s 64.251us 1 1 100.00
aes_core_fi 2.000s 162.741us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 138.477us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 120.638us 1 1 100.00
aes_stress 3.000s 64.251us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 64.251us 1 1 100.00
aes_sideload 2.000s 84.451us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 120.638us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 120.638us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 120.638us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 120.638us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 120.638us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 64.251us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 64.251us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 83.273us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 2.000s 83.273us 0 1 0.00
aes_control_fi 22.000s 10004.684us 0 1 0.00
aes_cipher_fi 2.000s 107.909us 1 1 100.00
aes_ctr_fi 2.000s 58.388us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 83.273us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 2.000s 83.273us 0 1 0.00
aes_control_fi 22.000s 10004.684us 0 1 0.00
aes_cipher_fi 2.000s 107.909us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 107.909us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 83.273us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 2.000s 83.273us 0 1 0.00
aes_control_fi 22.000s 10004.684us 0 1 0.00
aes_ctr_fi 2.000s 58.388us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 83.273us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 2.000s 83.273us 0 1 0.00
aes_control_fi 22.000s 10004.684us 0 1 0.00
aes_cipher_fi 2.000s 107.909us 1 1 100.00
aes_ctr_fi 2.000s 58.388us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 483.398us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 2.000s 83.273us 0 1 0.00
aes_control_fi 22.000s 10004.684us 0 1 0.00
aes_cipher_fi 2.000s 107.909us 1 1 100.00
aes_ctr_fi 2.000s 58.388us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 2.000s 83.273us 0 1 0.00
aes_control_fi 22.000s 10004.684us 0 1 0.00
aes_cipher_fi 2.000s 107.909us 1 1 100.00
aes_ctr_fi 2.000s 58.388us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 2.000s 83.273us 0 1 0.00
aes_control_fi 22.000s 10004.684us 0 1 0.00
aes_ctr_fi 2.000s 58.388us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 83.273us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 2.000s 83.273us 0 1 0.00
aes_control_fi 22.000s 10004.684us 0 1 0.00
aes_cipher_fi 2.000s 107.909us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 3.000s 148.734us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 33362643384983876106854994622427520920395216863940360810958583646730418569931 8830
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 4
----| Expected corrupted: 0
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 1 test run
aes_control_fi 28103218275262725043080291179159479062878975894822218229767020319924009356075 144
UVM_INFO @ 10004683777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 98608004108644342183911067776356183028923343395644209727061233010798064927160 210
UVM_INFO @ 148733746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---