Simulation Results: alert_handler

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.32 %
  • code
  • 90.30 %
  • assert
  • 98.31 %
  • func
  • 76.35 %
  • line
  • 99.72 %
  • branch
  • 97.99 %
  • cond
  • 90.59 %
  • toggle
  • 84.19 %
  • FSM
  • 79.03 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 45.650s 1474.101us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 5.540s 104.694us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 2.170s 68.471us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 178.260s 21675.067us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 72.680s 1822.417us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.770s 123.569us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 2.170s 68.471us 1 1 100.00
alert_handler_csr_aliasing 72.680s 1822.417us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 72.960s 3359.149us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 7.740s 447.391us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 783.180s 29469.728us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 20.450s 3018.651us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 45.650s 1474.101us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 7.500s 393.793us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 38.360s 4482.016us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 149.650s 6594.738us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 743.650s 15317.841us 1 1 100.00
alert_handler_lpg_stub_clk 588.920s 55795.407us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2133.650s 63612.889us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 8.430s 1223.370us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.700s 208.324us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.130s 8.345us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 6.400s 139.335us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 6.400s 139.335us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 5.540s 104.694us 1 1 100.00
alert_handler_csr_rw 2.170s 68.471us 1 1 100.00
alert_handler_csr_aliasing 72.680s 1822.417us 1 1 100.00
alert_handler_same_csr_outstanding 13.480s 1240.912us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 5.540s 104.694us 1 1 100.00
alert_handler_csr_rw 2.170s 68.471us 1 1 100.00
alert_handler_csr_aliasing 72.680s 1822.417us 1 1 100.00
alert_handler_same_csr_outstanding 13.480s 1240.912us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 108.410s 5036.294us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 108.410s 5036.294us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 108.410s 5036.294us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 108.410s 5036.294us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 173.890s 8527.684us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 15.840s 1964.830us 1 1 100.00
alert_handler_tl_intg_err 51.800s 1307.851us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 51.800s 1307.851us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 108.410s 5036.294us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 45.650s 1474.101us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 45.650s 1474.101us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 45.650s 1474.101us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 45.650s 1474.101us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 20.450s 3018.651us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 743.650s 15317.841us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 20.450s 3018.651us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 783.180s 29469.728us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 783.180s 29469.728us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.840s 1964.830us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.840s 1964.830us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.840s 1964.830us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.840s 1964.830us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 15.840s 1964.830us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.840s 1964.830us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.840s 1964.830us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.840s 1964.830us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 15.840s 1964.830us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 5.230s 226.762us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 22952445553090260636607166114568877346364694268139228789563896610796129307831 126
UVM_INFO @ 6594738175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 47475311521691602560637878476239214510006516745220741963395589440329290816234 202
UVM_INFO @ 1223370425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 112556883087898399265928104886058120895224347212412758566623892965288431093505 85
UVM_INFO @ 226761830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---