Simulation Results

Simulation Results: chip

30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
75.37 %

code
84.35 %

assert
97.49 %

func
44.27 %

line
94.37 %

branch
93.77 %

cond
89.08 %

toggle
87.38 %

FSM
57.14 %

Validation stages

V1		100.00%
V2		78.34%
V2S		50.00%
V3		69.23%
unmapped		63.64%

18/18 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	192.750s	3276.632us	1	1	100.00
	chip_sw_example_rom	75.640s	2782.382us	1	1	100.00
	chip_sw_example_manufacturer	142.430s	2496.251us	1	1	100.00
	chip_sw_example_concurrency	143.990s	2585.420us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	160.260s	4643.292us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	381.480s	5273.785us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	2632.830s	35799.862us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	5155.520s	37746.098us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	337.150s	6154.933us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	5155.520s	37746.098us	1	1	100.00
	chip_csr_rw	381.480s	5273.785us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	6.450s	46.632us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	302.360s	4843.622us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	302.360s	4843.622us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	302.360s	4843.622us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	385.950s	4935.301us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	385.950s	4935.301us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	392.830s	4644.986us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	390.680s	4376.139us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	330.310s	3827.099us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	1868.470s	12834.028us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	1028.100s	9190.452us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	331.890s	5014.667us	1	1	100.00

217/277 passed

78.34 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	144.490s	4204.182us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	144.490s	4204.182us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	206.160s	3478.032us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	314.150s	5498.979us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	235.190s	4184.637us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	116.800s	2938.927us	1	1	100.00
	chip_tap_straps_testunlock0	207.270s	5324.212us	1	1	100.00
	chip_tap_straps_rma	417.120s	6756.387us	1	1	100.00
	chip_tap_straps_prod	86.810s	2913.004us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	487.310s	5050.621us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	487.310s	5050.621us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	694.770s	8824.670us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	755.530s	9478.985us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	371.260s	3982.019us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	584.190s	5908.704us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4044.560s	19436.690us	1	1	100.00
	chip_sw_aes_enc_jitter_en	136.210s	3522.662us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	590.020s	6334.177us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	164.480s	3130.404us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1026.650s	10169.043us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	186.730s	3382.810us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	429.540s	4866.497us	1	1	100.00
	chip_sw_clkmgr_jitter	175.430s	3166.960us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	226.280s	3918.788us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	526.020s	7127.862us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	286.110s	4988.441us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	130.790s	2476.800us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	286.110s	4988.441us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	193.810s	3468.853us	1	1	100.00
	chip_sw_aes_smoketest	176.840s	3252.410us	1	1	100.00
	chip_sw_aon_timer_smoketest	238.660s	3339.604us	1	1	100.00
	chip_sw_clkmgr_smoketest	202.080s	2786.660us	1	1	100.00
	chip_sw_csrng_smoketest	180.290s	3368.302us	1	1	100.00
	chip_sw_entropy_src_smoketest	1030.100s	7799.135us	1	1	100.00
	chip_sw_gpio_smoketest	195.110s	3503.130us	1	1	100.00
	chip_sw_hmac_smoketest	248.860s	3194.619us	1	1	100.00
	chip_sw_kmac_smoketest	246.220s	3955.977us	1	1	100.00
	chip_sw_otbn_smoketest	1271.810s	8994.623us	1	1	100.00
	chip_sw_pwrmgr_smoketest	321.060s	7044.641us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	346.150s	6872.758us	1	1	100.00
	chip_sw_rv_plic_smoketest	172.440s	3359.859us	1	1	100.00
	chip_sw_rv_timer_smoketest	154.990s	2581.579us	1	1	100.00
	chip_sw_rstmgr_smoketest	151.300s	2993.250us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	167.940s	2685.110us	1	1	100.00
	chip_sw_uart_smoketest	154.480s	3390.937us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	173.380s	3042.948us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	384.460s	5734.867us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	8143.160s	63424.564us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3145.550s	14973.452us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	26.290s	0.000us	0	1	0.00
chip_sw_power_idle_load				1	1	100.00
	chip_sw_power_idle_load	443.320s	4489.261us	1	1	100.00
chip_sw_power_sleep_load				1	1	100.00
	chip_sw_power_sleep_load	290.980s	9374.129us	1	1	100.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7428.080s	55676.382us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7716.720s	59143.080us	1	1	100.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	52.340s	2578.892us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	52.340s	2578.892us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	5155.520s	37746.098us	1	1	100.00
	chip_same_csr_outstanding	1429.980s	14540.829us	1	1	100.00
	chip_csr_hw_reset	160.260s	4643.292us	1	1	100.00
	chip_csr_rw	381.480s	5273.785us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	5155.520s	37746.098us	1	1	100.00
	chip_same_csr_outstanding	1429.980s	14540.829us	1	1	100.00
	chip_csr_hw_reset	160.260s	4643.292us	1	1	100.00
	chip_csr_rw	381.480s	5273.785us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	37.530s	1682.740us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	5.420s	50.331us	1	1	100.00
	xbar_smoke_large_delays	48.620s	7948.933us	1	1	100.00
	xbar_smoke_slow_rsp	31.830s	3364.474us	1	1	100.00
	xbar_random_zero_delays	14.150s	131.943us	1	1	100.00
	xbar_random_large_delays	36.170s	6515.610us	1	1	100.00
	xbar_random_slow_rsp	259.100s	30617.803us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	10.890s	94.891us	1	1	100.00
	xbar_error_and_unmapped_addr	24.140s	911.627us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	20.620s	320.295us	1	1	100.00
	xbar_error_and_unmapped_addr	24.140s	911.627us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	13.740s	364.216us	1	1	100.00
	xbar_access_same_device_slow_rsp	232.480s	28657.905us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	46.670s	2143.768us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	278.420s	11702.072us	1	1	100.00
	xbar_stress_all_with_error	188.820s	3813.487us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	219.780s	885.975us	1	1	100.00
	xbar_stress_all_with_reset_error	237.240s	6029.403us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3145.550s	14973.452us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	2485.950s	27743.140us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3198.990s	16605.212us	1	1	100.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	123.533s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	34.757s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	7.758s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	13.479s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	11.678s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	45.752s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	60.199s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	54.268s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	35.375s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	20.944s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	137.747s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	97.689s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	135.376s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	137.447s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	92.045s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	24.520s	10.340us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	19.840s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	18.110s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	19.190s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	19.890s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	18.580s	10.140us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	19.880s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	19.410s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	18.500s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	19.810s	10.360us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	20.570s	10.380us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	19.070s	10.240us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	22.870s	10.360us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	19.140s	10.340us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.830s	10.160us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	52.695s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	104.698s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	9.980s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	111.004s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	9.433s	0.000us	0	1	0.00
rom_e2e_keymgr_init				2	3	66.67
	rom_e2e_keymgr_init_rom_ext_meas	6189.840s	29367.101us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_no_meas	3383.040s	18494.777us	0	1	0.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	6187.870s	30005.852us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3211.820s	16232.416us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3152.070s	34326.783us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3152.070s	34326.783us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	173.600s	3516.483us	1	1	100.00
	chip_sw_aes_enc_jitter_en	136.210s	3522.662us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	192.500s	3202.576us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	158.800s	2713.420us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	1750.890s	12863.520us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	142.720s	3070.596us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	440.640s	5837.987us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	405.420s	4339.464us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	582.870s	5225.951us	1	1	100.00
	chip_plic_all_irqs_10	263.590s	3178.286us	1	1	100.00
	chip_plic_all_irqs_20	417.650s	4573.990us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	199.420s	3181.048us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1118.170s	12228.266us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	304.360s	5099.861us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	112.120s	2166.041us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.135s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1012.060s	7997.485us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1135.390s	7907.510us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	825.630s	8489.359us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	7772.620s	255635.875us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	290.330s	4303.483us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	321.060s	7044.641us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	290.330s	4303.483us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	645.610s	8218.597us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	645.610s	8218.597us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	324.870s	6867.713us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	348.060s	5199.761us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	654.240s	5867.043us	1	1	100.00
	chip_sw_aes_idle	158.800s	2713.420us	1	1	100.00
	chip_sw_hmac_enc_idle	200.220s	3271.253us	1	1	100.00
	chip_sw_kmac_idle	167.380s	3290.832us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	253.670s	5039.199us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	333.650s	4895.387us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	295.090s	3916.592us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	277.950s	4785.198us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	667.970s	12544.887us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	349.560s	4229.015us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	359.260s	5195.114us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	354.470s	4446.918us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	387.310s	5181.920us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	356.890s	4801.782us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	419.150s	4547.230us	1	1	100.00
	chip_sw_ast_clk_outputs	694.770s	8824.670us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	658.620s	10266.104us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	354.470s	4446.918us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	387.310s	5181.920us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	371.260s	3982.019us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	584.190s	5908.704us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4044.560s	19436.690us	1	1	100.00
	chip_sw_aes_enc_jitter_en	136.210s	3522.662us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	590.020s	6334.177us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	164.480s	3130.404us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1026.650s	10169.043us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	186.730s	3382.810us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	429.540s	4866.497us	1	1	100.00
	chip_sw_clkmgr_jitter	175.430s	3166.960us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	138.880s	3119.852us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	345.030s	5042.158us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	657.220s	7256.718us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4268.670s	24927.227us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	147.430s	2848.354us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	189.140s	3568.392us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	1249.550s	11871.034us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	191.870s	3844.977us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	346.320s	5749.153us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1238.140s	20652.111us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	3739.850s	26101.376us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	694.770s	8824.670us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	353.970s	5109.968us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	265.920s	3412.062us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	405.420s	4339.464us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1012.060s	7997.485us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	1977.980s	23948.821us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				0	1	0.00
	chip_sw_csrng_fuse_en_sw_app_read_test	205.420s	3640.998us	0	1	0.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	545.790s	6060.038us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	142.170s	2730.167us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	2367.820s	15482.996us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	152.660s	2961.698us	1	1	100.00
	chip_sw_edn_entropy_reqs	770.300s	7186.399us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	152.660s	2961.698us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	1977.980s	23948.821us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	140.890s	2957.173us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1032.950s	18124.223us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	545.210s	5721.108us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	584.190s	5908.704us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	422.750s	4976.959us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	371.260s	3982.019us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3585.270s	42942.835us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1032.950s	18124.223us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	203.040s	3633.568us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	1447.780s	11530.332us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	145.660s	3600.222us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3585.270s	42942.835us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	145.660s	3600.222us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	145.660s	3600.222us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	145.660s	3600.222us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	145.660s	3600.222us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	405.420s	4339.464us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	187.300s	6544.995us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	586.670s	5558.216us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	377.960s	5990.041us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	377.960s	5990.041us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	163.200s	2629.810us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	164.480s	3130.404us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	200.220s	3271.253us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	656.030s	6138.303us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1941.920s	12018.522us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	443.760s	4446.657us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	474.470s	5577.071us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	363.660s	5253.276us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	292.770s	3998.437us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	1447.780s	11530.332us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1026.650s	10169.043us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1748.620s	12645.851us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	1750.890s	12863.520us	1	1	100.00
chip_sw_keymgr_sideload_otbn				0	1	0.00
	chip_sw_keymgr_sideload_otbn	4215.750s	20026.813us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	141.730s	3191.710us	1	1	100.00
	chip_sw_kmac_mode_kmac	146.180s	2775.454us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	186.730s	3382.810us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	1447.780s	11530.332us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	686.440s	12357.091us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	148.020s	3316.677us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	984.460s	7477.389us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	167.380s	3290.832us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	440.640s	5837.987us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	116.800s	2938.927us	1	1	100.00
	chip_tap_straps_rma	417.120s	6756.387us	1	1	100.00
	chip_tap_straps_prod	86.810s	2913.004us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	149.320s	3573.593us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	686.440s	12357.091us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	686.440s	12357.091us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	686.440s	12357.091us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1188.970s	9812.503us	1	1	100.00
chip_sw_lc_ctrl_broadcast				20	22	90.91
	chip_sw_flash_ctrl_lc_rw_en	145.660s	3600.222us	0	1	0.00
	chip_sw_flash_rma_unlocked	3585.270s	42942.835us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	210.530s	3261.639us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	513.010s	6550.653us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	561.760s	6255.538us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	571.080s	6378.454us	0	1	0.00
	chip_sw_lc_ctrl_transition	686.440s	12357.091us	1	1	100.00
	chip_sw_keymgr_key_derivation	1447.780s	11530.332us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	407.600s	9336.599us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	450.250s	7635.962us	1	1	100.00
	chip_prim_tl_access	187.300s	6544.995us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	658.620s	10266.104us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	349.560s	4229.015us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	359.260s	5195.114us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	354.470s	4446.918us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	387.310s	5181.920us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	356.890s	4801.782us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	419.150s	4547.230us	1	1	100.00
	chip_tap_straps_dev	116.800s	2938.927us	1	1	100.00
	chip_tap_straps_rma	417.120s	6756.387us	1	1	100.00
	chip_tap_straps_prod	86.810s	2913.004us	1	1	100.00
	chip_rv_dm_lc_disabled	216.490s	7080.602us	1	1	100.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	146.130s	3403.767us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	79.420s	3674.323us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	96.420s	3149.867us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	87.800s	3725.383us	1	1	100.00
chip_lc_test_locked				2	2	100.00
	chip_sw_lc_walkthrough_testunlocks	1385.550s	23889.369us	1	1	100.00
	chip_rv_dm_lc_disabled	216.490s	7080.602us	1	1	100.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	658.690s	11946.899us	0	1	0.00
	chip_sw_lc_walkthrough_prod	730.730s	11331.642us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	583.580s	7936.758us	1	1	100.00
	chip_sw_lc_walkthrough_rma	365.560s	5392.831us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1385.550s	23889.369us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	76.480s	2770.266us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	60.230s	2067.371us	1	1	100.00
	rom_volatile_raw_unlock	23.417s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3870.020s	17536.521us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4044.560s	19436.690us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	654.240s	5867.043us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	654.240s	5867.043us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	654.240s	5867.043us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	317.630s	3593.169us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	686.440s	12357.091us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1032.950s	18124.223us	1	1	100.00
	chip_sw_otbn_mem_scramble	317.630s	3593.169us	1	1	100.00
	chip_sw_keymgr_key_derivation	1447.780s	11530.332us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	308.260s	4652.396us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	201.010s	3675.594us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1032.950s	18124.223us	1	1	100.00
	chip_sw_otbn_mem_scramble	317.630s	3593.169us	1	1	100.00
	chip_sw_keymgr_key_derivation	1447.780s	11530.332us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	308.260s	4652.396us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	201.010s	3675.594us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	686.440s	12357.091us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	308.870s	4782.492us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	149.320s	3573.593us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	210.530s	3261.639us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	513.010s	6550.653us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	561.760s	6255.538us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	571.080s	6378.454us	0	1	0.00
	chip_sw_lc_ctrl_transition	686.440s	12357.091us	1	1	100.00
	chip_prim_tl_access	187.300s	6544.995us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	187.300s	6544.995us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	829.770s	7879.388us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	185.030s	5452.268us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	922.450s	24440.596us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	236.380s	7357.679us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_por_reset	386.250s	7418.899us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	432.840s	7426.706us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	1171.300s	26428.220us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				1	2	50.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	474.650s	10038.525us	0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	645.610s	8218.597us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	1017.720s	12626.537us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	387.140s	5167.455us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	185.030s	5452.268us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	347.750s	5323.300us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	813.390s	15046.706us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	371.910s	6670.718us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	158.920s	2915.082us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	586.840s	11940.612us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	506.920s	7942.878us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	890.160s	12049.710us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	2101.300s	34648.887us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	192.320s	3135.601us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	405.420s	4339.464us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	407.600s	9336.599us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	407.600s	9336.599us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	890.160s	12049.710us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	586.840s	11940.612us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	387.140s	5167.455us	1	1	100.00
	chip_sw_pwrmgr_smoketest	321.060s	7044.641us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	223.780s	3269.980us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	516.780s	6452.705us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	242.950s	3954.169us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1118.170s	12228.266us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	199.050s	3141.768us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	405.420s	4339.464us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1135.390s	7907.510us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	505.830s	4887.903us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	490.200s	4703.924us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	175.550s	3272.041us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	201.010s	3675.594us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	516.780s	6452.705us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	516.780s	6452.705us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	131.180s	2530.193us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	765.080s	8725.146us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	818.270s	14217.937us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	223.780s	3269.980us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	200.730s	3422.327us	0	1	0.00
chip_rv_dm_access_after_wakeup				1	1	100.00
	chip_sw_rv_dm_access_after_wakeup	364.710s	6494.458us	1	1	100.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	417.120s	6756.387us	1	1	100.00
chip_rv_dm_lc_disabled				1	1	100.00
	chip_rv_dm_lc_disabled	216.490s	7080.602us	1	1	100.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	582.870s	5225.951us	1	1	100.00
	chip_plic_all_irqs_10	263.590s	3178.286us	1	1	100.00
	chip_plic_all_irqs_20	417.650s	4573.990us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	171.770s	2743.833us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	184.430s	3686.042us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3145.550s	14973.452us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	419.340s	6049.521us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	218.740s	3640.292us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	178.570s	2602.121us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	154.400s	2945.960us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	308.260s	4652.396us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	429.540s	4866.497us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	415.920s	7439.285us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	523.110s	7892.696us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	450.250s	7635.962us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	405.420s	4339.464us	1	1	100.00
	chip_sw_data_integrity_escalation	487.310s	5050.621us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	506.920s	7942.878us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	981.020s	23150.395us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	134.400s	2863.745us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	258.790s	4169.519us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	336.280s	5017.129us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	981.020s	23150.395us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	981.020s	23150.395us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2307.850s	20797.502us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2307.850s	20797.502us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	236.360s	5253.417us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3152.070s	34326.783us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	136.590s	2607.270us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	170.620s	3100.013us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	253.960s	3697.238us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	348.830s	3936.434us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	959.510s	8284.112us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5691.200s	31861.002us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	2004.330s	12208.772us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	203.350s	2964.681us	1	1	100.00

V2S

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	220.750s	3601.417us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				0	1	0.00
	chip_sw_rv_core_ibex_lockstep_glitch	111.510s	2956.599us	0	1	0.00

18/26 passed

69.23 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	10330.490s	71986.627us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1094.610s	6750.164us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	173.870s	4258.017us	0	1	0.00
	rom_e2e_jtag_debug_dev	444.980s	6829.718us	0	1	0.00
	rom_e2e_jtag_debug_rma	485.270s	6710.304us	0	1	0.00
rom_e2e_jtag_inject				1	3	33.33
	rom_e2e_jtag_inject_test_unlocked0	229.260s	5832.800us	1	1	100.00
	rom_e2e_jtag_inject_dev	55.960s	1930.764us	0	1	0.00
	rom_e2e_jtag_inject_rma	49.820s	1904.478us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	31.232s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	261.250s	3830.976us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	306.700s	3361.986us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	700.370s	4483.348us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	927.200s	7183.841us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	226.860s	2740.433us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	659.780s	6013.627us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	58.150s	2877.268us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	200.950s	3268.462us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	301.030s	5864.662us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	384.820s	5088.031us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	890.160s	12049.710us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	173.870s	4258.017us	0	1	0.00
	rom_e2e_jtag_debug_dev	444.980s	6829.718us	0	1	0.00
	rom_e2e_jtag_debug_rma	485.270s	6710.304us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	386.260s	5800.096us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	405.420s	4339.464us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5751.340s	38028.865us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5751.340s	38028.865us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	175.490s	3851.089us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	385.950s	4935.301us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3118.600s	18665.136us	1	1	100.00

unmapped

7/11 passed

63.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	11	63.64
	chip_sival_flash_info_access	210.320s	3608.729us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	24.960s	10.100us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	4.990s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	113.410s	2449.933us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	183.350s	2763.475us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	289.190s	4041.781us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	8.029s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	240.070s	3959.340us	1	1	100.00
	ate_bootstrap_flash_erase	623.810s	10010.360us	0	1	0.00
	ate_bootstrap_one_frame	6817.090s	45112.411us	1	1	100.00
	ate_bootstrap_disjoint	9861.040s	85195.140us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	84450683132348704714273830991817152873410517731514213499758634564949797706233	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	79258756613363675340146353024567404556469820420237701039404369557720423686040	None	Another command (pid=581864) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=587715) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=382187) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	109561295488030179554822248235714669854834238847955220200498549763932454327607	None	Another command (pid=630073) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=631120) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=580879) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	113397699046879734610058600403551369033593857086264010865021210630184103031816	None	---- STDERR ---- Another command (pid=589797) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	113817921506830236881872027413396882917888768018360865198125291902359491940010	None	Another command (pid=567735) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=456684) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=484409) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	85150322663270473614708641202419701537037556272354956903644403796347658270015	None	---- STDERR ---- Another command (pid=567735) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	28996856534333993809897156661499360892249581889294585564049382015918283692641	None	Another command (pid=416216) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=452351) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=396791) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	81030978133708309992197117214931636528597160744744727500577014201344224423600	None	---- STDERR ---- Another command (pid=467608) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	59452039571680784384181124926040682568174492676864513627411143753875683051199	None	Another command (pid=434536) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=465402) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=464739) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16058912059872647736067175843457898962298545353422664384003718408342662651096	None	Another command (pid=484520) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=466619) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=468755) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	100327304431330311825766232822641695494254210510603014908950574566496633197078	None	Another command (pid=592831) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=447857) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=595936) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	65541420116760896666391019497818676457019441444859318624042406672809822002441	None	Another command (pid=599515) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=567735) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=484409) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	111505200807556408596606329544032554246752317390734652736030001379566176775989	None	Another command (pid=622591) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=629010) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=630073) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	2776057643523228492071866707334550482147442055144330681368378666534664073393	None	Another command (pid=701407) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=712146) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=687366) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	6051279402415028909979206981854101853998835284523739771588917442419313911667	None	Another command (pid=719399) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=707521) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=713201) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	86498827570146932714487963670824057111434498444395254755133119727610818848281	None	---- STDERR ---- Another command (pid=594091) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	115262568389019254390743457499380106756925671713756631189137338055975005897637	None	Another command (pid=393997) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=416216) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=452351) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	20769355511169242321984566080303631941499008163978432375308971932854363275351	None	Another command (pid=482856) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=595473) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=567735) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	72737026970307565833846199207862989437703201132164939421634552422879340169570	None	---- STDERR ---- Another command (pid=416216) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=452351) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	57082592474611485671795484586447078138711038569591348059644968307544333315472	None	Another command (pid=577530) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=639310) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=639547) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	88810511338476560454367501355697753538262900066067707129496188350805383781062	None	Another command (pid=416216) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=452351) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=463603) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	75705965012656526453405329540465757853740835693288851702604466712152549910378	None	---- STDERR ---- Another command (pid=380442) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=415893) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	33944000696129300258080140073994584743616334070450269709926936288647886079638	None	---- STDERR ---- Another command (pid=380442) is running. Waiting for it to complete on the server (server_pid=271774)... Another command (pid=442964) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	101602439548618642132524705782497294604011288920250799893654723263403917404078	None	---- STDERR ---- Another command (pid=380442) is running. Waiting for it to complete on the server (server_pid=271774)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access				6 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	48174192756368353886772363188353881851452744833372730156947896197810768660470	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_test_unlocked0	107616136571704791040734130446727445839629444885881207257931203434362468933911	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	32628411335761119621512941384569957207739620930599311745153151615335133891115	352	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	9267111891120943785943317470094510792264259433544649182260904179294729753061	352	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	71121673492750394663275130807536592465772427962197736353054555326043353584285	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	68192797016771343439956814159428419269864414632167436489902757682828669426863	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	55701421365272835410563674532687570576730047795847168613421857873770647060577	367	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	70824124601652777956249684304829096844791227727513929382756798402044215979122	367	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	32975706260328690380534976906364012735941224528456614067793129659519502421014	367	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	46065096538746133228138992887438521338050904917751448042030380818635207653200	328	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	109236467284753305428501426081479709443690565056324391751383144175594989595611	327	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	107601146114237647885681525214084776784079734674940079617986923163581908590912	327	UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	6648504625777416324933205896223292706923110981365470632062090125780084046580	369	UVM_INFO @ 11946.898917 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	66034187997239817477709708129527550649279539586411425758227241970048515834938	369	UVM_INFO @ 11331.641870 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	53707108278947765559529640706986725984326526432502282934562000173889230143731	341	UVM_INFO @ 5392.830598 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				3 test runs
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	98950585859589565746620937298663493482125988232362445244799495077172977961361	344	UVM_ERROR @ 11940.612000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 11940.612000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	68063314187516787461466577268104338628160566968008111332766284494874914808146	327	UVM_ERROR @ 10038.525500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 10038.525500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	62305465982438758803911912042393041558356602073134659111567228773000359344269	353	UVM_ERROR @ 15046.706000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 15046.706000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	100088457852147632424226082454314323969524870256830408676958900195866005153471	325	UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	80578199330136206269280276541087344421216922139436278116997245432797534813242	328	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	32455126193138091607390552464581713282808376919583172082211271524144761494449	328	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				2 test runs
	chip_sw_otp_ctrl_escalation	29016355373688875174337519439882171817797517733277938440852647608326715885162	316	UVM_ERROR @ 3268.462296 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3268.462296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_csrng_fuse_en_sw_app_read_test	18311136845604796716215869792619656687200318522320457034805590519728182340344	312	UVM_ERROR @ 3640.997526 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3640.997526 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				2 test runs
	chip_sw_hmac_multistream	99403252173172300009952901384907123071765438067018584043996845256557191480339	382	UVM_INFO @ 12018.521764 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_keymgr_sideload_otbn	958238820447621457640564762257410717262802591083001833263789155154732014029	334	UVM_INFO @ 20026.812862 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	101341075720269293089493707573753546873470167078772269251833002289570294293030	363	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	84241369399370070048650136239269333818112963777358945410331161010069621203580	325	UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	108618152508723389631924192946721284525254769604770078142131408522839671804781	367	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	97622971448305427375944259239835028589551519207450232354472389716083604773412	326	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr_aon.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	85170431977586173171782000466265094489721662586947168229679331666778347232009	301	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	6374691846008598646557059642336757907886049288318973016242688584100136152020	327	UVM_INFO @ 3640.291912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	35583256326434407618926346987314476534916993560801288386803943466217789614551	309	UVM_INFO @ 3600.221924 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	11430190291694919178916347386846634535268622041779753854359256143692945468811	342	UVM_INFO @ 6378.453601 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	64658407137473633045036987604918088005155234629638296951404452972388653775844	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	82397455681545661922413698508301280011536960162803612526769555714284885539009	320	UVM_ERROR @ 5452.267910 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 5452.267910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				1 test run
	chip_sw_pwrmgr_sleep_power_glitch_reset	87303087849481434703797380208053510514370685121679662001265361884160487039678	313	UVM_ERROR @ 2915.082485 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 2915.082485 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	16512623918955068675192551973280918929142238733403022953351936457976072087866	332	UVM_INFO @ 34326.783055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:297)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	4877413355111152297819477256946948485975705571404620138850541608268058802705	307	UVM_INFO @ 3070.595937 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	29896372434847306928638651682835858649165696514357224169286947940567247729452	308	UVM_INFO @ 2166.041400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	96855387422675892390152365620524784517041084047294726332176473983292738934876	None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).				1 test run
	chip_tl_errors	111268172463788648494266343777263347893194950410362374262032190798240537114425	217	TL item was: req: (cip_tl_seq_item@34048) { a_addr: 'h104ec a_data: 'h8187a4c2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd a_opcode: 'h4 a_user: 'h18d19 d_param: 'h0 d_source: 'hd d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2578.892040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	26890675337203986913037095480968915208980197547170297084949138045918139586815	343	UVM_INFO @ 3830.976368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [] vs [*]) Major alert did not match expectation.				1 test run
	chip_sw_rv_core_ibex_lockstep_glitch	19649162404271691314339577604485897795370134905406709850926774908732196550097	322	UVM_INFO @ 2956.599138 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	47856813971825757427867574944786637656925823947870398166594934100603205030103	327	UVM_INFO @ 9478.985107 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	15193136464344358319674986044194269684632976798783071343904615736068702989240	272	UVM_INFO @ 10010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	1181206152270913562329254953265650199422038545237262784068831396671297260599	325	UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	72133955360375285048226328163340419244501610774968089198247117698981134677894	325	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *				1 test run
	rom_e2e_keymgr_init_rom_ext_no_meas	76171561764140919097676444573087163838339785828502278065337008325702045027973	319	UVM_INFO @ 18494.777124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	9133846406840755975040918784133796101215755390910127548330453057358355115970	327	UVM_ERROR @ 5734.866520 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 5734.866520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---