Simulation Results: clkmgr

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.46 %
  • code
  • 97.41 %
  • assert
  • 93.08 %
  • func
  • 83.88 %
  • line
  • 98.83 %
  • branch
  • 98.32 %
  • cond
  • 89.88 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.760s 27.416us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.990s 42.673us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.770s 16.130us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 14.150s 5321.881us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.460s 66.889us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.200s 32.903us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.770s 16.130us 1 1 100.00
clkmgr_csr_aliasing 1.460s 66.889us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.690s 28.999us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.840s 102.247us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.950s 26.147us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.130s 171.279us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.760s 27.416us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 5.920s 1162.438us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 3.430s 1283.677us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 5.920s 1162.438us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 1.120s 197.054us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.860s 27.660us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.240s 139.598us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.240s 139.598us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.990s 42.673us 1 1 100.00
clkmgr_csr_rw 0.770s 16.130us 1 1 100.00
clkmgr_csr_aliasing 1.460s 66.889us 1 1 100.00
clkmgr_same_csr_outstanding 1.650s 442.595us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.990s 42.673us 1 1 100.00
clkmgr_csr_rw 0.770s 16.130us 1 1 100.00
clkmgr_csr_aliasing 1.460s 66.889us 1 1 100.00
clkmgr_same_csr_outstanding 1.650s 442.595us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
clkmgr_sec_cm 2.460s 732.832us 1 1 100.00
clkmgr_tl_intg_err 1.360s 147.832us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 352.390s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 352.390s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 352.390s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 352.390s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 740.830s 200000.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.360s 147.832us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 5.920s 1162.438us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 3.430s 1283.677us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 352.390s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.170s 181.523us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.950s 31.267us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.750s 38.663us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.870s 103.774us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.900s 80.352us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.770s 16.130us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 2.460s 732.832us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.770s 16.130us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.770s 16.130us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 2.460s 732.832us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 0.960s 54.574us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 38.970s 14795.852us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
clkmgr_shadow_reg_errors 114942821488147067644665977345556690870010824077167248509809453644805367399224 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 34271173642806728333864085109770131158957583653560493839365981727988741378957 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---