Simulation Results: edn/edn0

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.49 %
  • code
  • 85.46 %
  • assert
  • 98.26 %
  • func
  • 81.75 %
  • line
  • 98.37 %
  • branch
  • 94.70 %
  • cond
  • 89.20 %
  • toggle
  • 91.80 %
  • FSM
  • 53.23 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.840s 20.173us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.930s 16.975us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.980s 13.820us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.210s 679.952us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.080s 96.153us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.460s 281.551us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.980s 13.820us 1 1 100.00
edn_csr_aliasing 1.080s 96.153us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.230s 131.206us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.230s 131.206us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.230s 131.206us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.910s 23.181us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.230s 95.883us 1 1 100.00
errs 1 1 100.00
edn_err 1.110s 30.912us 1 1 100.00
disable 2 2 100.00
edn_disable 0.950s 20.801us 1 1 100.00
edn_disable_auto_req_mode 1.040s 88.494us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.640s 532.297us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.740s 35.705us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.170s 28.413us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.040s 733.010us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.040s 733.010us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.930s 16.975us 1 1 100.00
edn_csr_rw 0.980s 13.820us 1 1 100.00
edn_csr_aliasing 1.080s 96.153us 1 1 100.00
edn_same_csr_outstanding 1.090s 124.226us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.930s 16.975us 1 1 100.00
edn_csr_rw 0.980s 13.820us 1 1 100.00
edn_csr_aliasing 1.080s 96.153us 1 1 100.00
edn_same_csr_outstanding 1.090s 124.226us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.290s 2795.415us 1 1 100.00
edn_tl_intg_err 1.870s 87.872us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.790s 30.047us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.230s 95.883us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.290s 2795.415us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.290s 2795.415us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.290s 2795.415us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.290s 2795.415us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.230s 95.883us 1 1 100.00
edn_sec_cm 7.290s 2795.415us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.230s 95.883us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.870s 87.872us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 66.750s 15282.812us 1 1 100.00