Simulation Results: edn/edn1

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.27 %
  • code
  • 83.92 %
  • assert
  • 98.70 %
  • func
  • 79.20 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 88.62 %
  • toggle
  • 94.99 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.930s 20.209us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.820s 15.218us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.720s 21.563us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.770s 775.269us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.970s 43.862us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.820s 49.408us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.720s 21.563us 1 1 100.00
edn_csr_aliasing 0.970s 43.862us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.230s 36.729us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.230s 36.729us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.230s 36.729us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.830s 21.846us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.980s 36.034us 1 1 100.00
errs 1 1 100.00
edn_err 0.900s 36.045us 1 1 100.00
disable 2 2 100.00
edn_disable 0.760s 12.135us 1 1 100.00
edn_disable_auto_req_mode 0.870s 60.440us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.590s 199.887us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.850s 27.324us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.780s 26.734us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.660s 62.547us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.660s 62.547us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.820s 15.218us 1 1 100.00
edn_csr_rw 0.720s 21.563us 1 1 100.00
edn_csr_aliasing 0.970s 43.862us 1 1 100.00
edn_same_csr_outstanding 0.900s 28.643us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.820s 15.218us 1 1 100.00
edn_csr_rw 0.720s 21.563us 1 1 100.00
edn_csr_aliasing 0.970s 43.862us 1 1 100.00
edn_same_csr_outstanding 0.900s 28.643us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.090s 580.090us 1 1 100.00
edn_tl_intg_err 1.460s 79.683us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.820s 20.745us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.980s 36.034us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.090s 580.090us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.090s 580.090us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.090s 580.090us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.090s 580.090us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.980s 36.034us 1 1 100.00
edn_sec_cm 2.090s 580.090us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.980s 36.034us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.460s 79.683us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 28.210s 4031.361us 1 1 100.00