Simulation Results: flash_ctrl

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.46 %
  • code
  • 93.05 %
  • assert
  • 94.55 %
  • func
  • 95.79 %
  • line
  • 95.90 %
  • branch
  • 96.69 %
  • cond
  • 93.34 %
  • toggle
  • 94.96 %
  • FSM
  • 84.35 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.83%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 49.290s 92.728us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 12.820s 29.876us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 14.140s 39.221us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 7.120s 299.162us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 41.310s 3926.293us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 42.280s 3483.859us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 6.850s 92.856us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 7.120s 299.162us 1 1 100.00
flash_ctrl_csr_aliasing 42.280s 3483.859us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 7.820s 63.974us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.320s 31.013us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 11.670s 23.062us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 35.080s 52.097us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1376.110s 250862.810us 1 1 100.00
flash_ctrl_hw_rma_reset 546.450s 210241.848us 1 1 100.00
flash_ctrl_lcmgr_intg 6.420s 26.867us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1128.630s 2030492.148us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 151.610s 3205.010us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 7.080s 273.260us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1942.580s 419480.913us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 40.950s 56.152us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 16.150s 30.585us 1 1 100.00
flash_ctrl_rw_evict_all_en 15.080s 74.790us 1 1 100.00
flash_ctrl_re_evict 15.620s 143.907us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 25.670s 28.373us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 25.670s 28.373us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 362.060s 21705.418us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 15.570s 1832.472us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 308.120s 533.024us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 397.170s 3558.114us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 356.730s 4216.581us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 986.120s 1248.177us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 7.240s 237.729us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 178.140s 18906.401us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.920s 82.767us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.350s 29.233us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 78.700s 89.966us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 32.510s 3170.770us 1 1 100.00
flash_ctrl_otp_reset 61.800s 141.219us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1376.110s 250862.810us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 91.550s 1136.920us 1 1 100.00
flash_ctrl_intr_wr 44.990s 4735.371us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 75.900s 5891.850us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 98.780s 20920.190us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 39.670s 7479.741us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 42.090s 2093.265us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 12.850s 29.769us 1 1 100.00
flash_ctrl_ro_derr 96.850s 910.365us 1 1 100.00
flash_ctrl_rw_derr 118.890s 1604.688us 1 1 100.00
flash_ctrl_derr_detect 96.400s 694.452us 1 1 100.00
flash_ctrl_integrity 361.480s 20039.571us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.750s 105.417us 1 1 100.00
flash_ctrl_ro_serr 110.100s 11035.576us 1 1 100.00
flash_ctrl_rw_serr 133.900s 3664.209us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 57.800s 4466.580us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 44.800s 3040.573us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 141.390s 24933.130us 1 1 100.00
flash_ctrl_write_word_sweep 7.280s 49.128us 1 1 100.00
flash_ctrl_read_word_sweep 7.040s 30.959us 1 1 100.00
flash_ctrl_ro 74.290s 1762.995us 1 1 100.00
flash_ctrl_rw 352.810s 4333.468us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 22.300s 3197.215us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 745.740s 102185.467us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 68.930s 10020.507us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.800s 57.399us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.470s 33.348us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.960s 222.279us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.960s 222.279us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 14.140s 39.221us 1 1 100.00
flash_ctrl_csr_rw 7.120s 299.162us 1 1 100.00
flash_ctrl_csr_aliasing 42.280s 3483.859us 1 1 100.00
flash_ctrl_same_csr_outstanding 10.040s 1128.427us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 14.140s 39.221us 1 1 100.00
flash_ctrl_csr_rw 7.120s 299.162us 1 1 100.00
flash_ctrl_csr_aliasing 42.280s 3483.859us 1 1 100.00
flash_ctrl_same_csr_outstanding 10.040s 1128.427us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 10.950s 18.966us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 10.950s 18.966us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 10.950s 18.966us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 10.950s 18.966us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 24.860s 452.214us 1 1 100.00
tl_intg_err 1 2 50.00
flash_ctrl_sec_cm 3267.820s 200000.000us 0 1 0.00
flash_ctrl_tl_intg_err 403.300s 1638.529us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 403.300s 1638.529us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 403.300s 1638.529us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 15.750s 77.229us 1 1 100.00
flash_ctrl_wr_intg 7.030s 109.248us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 49.290s 92.728us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 61.800s 141.219us 1 1 100.00
flash_ctrl_disable 10.920s 82.767us 1 1 100.00
flash_ctrl_sec_info_access 50.640s 3268.397us 1 1 100.00
flash_ctrl_connect 7.350s 29.233us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.830s 39.115us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.120s 299.162us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 10.950s 18.966us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.120s 299.162us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 10.950s 18.966us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.120s 299.162us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 10.950s 18.966us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.920s 82.767us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 15.750s 77.229us 1 1 100.00
flash_ctrl_access_after_disable 7.400s 83.290us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 12.630s 27.964us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.920s 82.767us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 15.570s 1832.472us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 352.810s 4333.468us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 133.900s 3664.209us 1 1 100.00
flash_ctrl_rw_derr 118.890s 1604.688us 1 1 100.00
flash_ctrl_integrity 361.480s 20039.571us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1376.110s 250862.810us 1 1 100.00
sec_cm_ctrl_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 3267.820s 200000.000us 0 1 0.00
sec_cm_phy_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 3267.820s 200000.000us 0 1 0.00
sec_cm_phy_prog_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 3267.820s 200000.000us 0 1 0.00
sec_cm_ctr_redun 0 1 0.00
flash_ctrl_sec_cm 3267.820s 200000.000us 0 1 0.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 11.120s 825.296us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.620s 83.094us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 8.210s 23.089us 1 1 100.00
sec_cm_fifo_ctr_redun 0 1 0.00
flash_ctrl_sec_cm 3267.820s 200000.000us 0 1 0.00
sec_cm_mem_tl_lc_gate_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 3267.820s 200000.000us 0 1 0.00
sec_cm_prog_tl_lc_gate_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 3267.820s 200000.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 25.390s 84.801us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 313.780s 720.192us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue 1 test run
flash_ctrl_sec_cm 109382058424064351263056282953182209034936633552090183144131138487909308662426 5478
UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---