Simulation Results: hmac

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.01 %
  • code
  • 97.41 %
  • assert
  • 97.38 %
  • func
  • 42.24 %
  • line
  • 99.54 %
  • branch
  • 98.51 %
  • cond
  • 95.11 %
  • toggle
  • 99.77 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.020s 983.083us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.800s 81.887us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.940s 21.631us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.060s 948.444us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.560s 421.273us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.570s 48.867us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.940s 21.631us 1 1 100.00
hmac_csr_aliasing 5.560s 421.273us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 61.960s 30092.890us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 48.290s 2077.867us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 9.030s 1034.369us 1 1 100.00
hmac_test_sha384_vectors 20.470s 302.907us 1 1 100.00
hmac_test_sha512_vectors 348.760s 119495.529us 1 1 100.00
hmac_test_hmac256_vectors 10.590s 1989.008us 1 1 100.00
hmac_test_hmac384_vectors 7.630s 1192.731us 1 1 100.00
hmac_test_hmac512_vectors 9.230s 360.824us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 9.610s 1465.223us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 445.870s 48487.606us 1 1 100.00
error 1 1 100.00
hmac_error 73.140s 7391.670us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 32.840s 2076.094us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.020s 983.083us 1 1 100.00
hmac_long_msg 61.960s 30092.890us 1 1 100.00
hmac_back_pressure 48.290s 2077.867us 1 1 100.00
hmac_datapath_stress 445.870s 48487.606us 1 1 100.00
hmac_burst_wr 9.610s 1465.223us 1 1 100.00
hmac_stress_all 13.000s 2102.336us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.020s 983.083us 1 1 100.00
hmac_long_msg 61.960s 30092.890us 1 1 100.00
hmac_back_pressure 48.290s 2077.867us 1 1 100.00
hmac_datapath_stress 445.870s 48487.606us 1 1 100.00
hmac_wipe_secret 32.840s 2076.094us 1 1 100.00
hmac_test_sha256_vectors 9.030s 1034.369us 1 1 100.00
hmac_test_sha384_vectors 20.470s 302.907us 1 1 100.00
hmac_test_sha512_vectors 348.760s 119495.529us 1 1 100.00
hmac_test_hmac256_vectors 10.590s 1989.008us 1 1 100.00
hmac_test_hmac384_vectors 7.630s 1192.731us 1 1 100.00
hmac_test_hmac512_vectors 9.230s 360.824us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.020s 983.083us 1 1 100.00
hmac_long_msg 61.960s 30092.890us 1 1 100.00
hmac_back_pressure 48.290s 2077.867us 1 1 100.00
hmac_datapath_stress 445.870s 48487.606us 1 1 100.00
hmac_burst_wr 9.610s 1465.223us 1 1 100.00
hmac_error 73.140s 7391.670us 1 1 100.00
hmac_wipe_secret 32.840s 2076.094us 1 1 100.00
hmac_test_sha256_vectors 9.030s 1034.369us 1 1 100.00
hmac_test_sha384_vectors 20.470s 302.907us 1 1 100.00
hmac_test_sha512_vectors 348.760s 119495.529us 1 1 100.00
hmac_test_hmac256_vectors 10.590s 1989.008us 1 1 100.00
hmac_test_hmac384_vectors 7.630s 1192.731us 1 1 100.00
hmac_test_hmac512_vectors 9.230s 360.824us 1 1 100.00
hmac_stress_all 13.000s 2102.336us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 13.000s 2102.336us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.600s 15.889us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.650s 138.071us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.350s 247.560us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.350s 247.560us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.800s 81.887us 1 1 100.00
hmac_csr_rw 0.940s 21.631us 1 1 100.00
hmac_csr_aliasing 5.560s 421.273us 1 1 100.00
hmac_same_csr_outstanding 1.520s 129.245us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.800s 81.887us 1 1 100.00
hmac_csr_rw 0.940s 21.631us 1 1 100.00
hmac_csr_aliasing 5.560s 421.273us 1 1 100.00
hmac_same_csr_outstanding 1.520s 129.245us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.040s 107.146us 1 1 100.00
hmac_tl_intg_err 2.580s 329.377us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.580s 329.377us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.020s 983.083us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.350s 110.798us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 51.790s 52823.751us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 6.120s 732.735us 1 1 100.00