Simulation Results

Simulation Results: i2c

30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.13 %

code
78.34 %

assert
97.25 %

func
79.81 %

line
96.38 %

branch
92.26 %

cond
84.86 %

toggle
74.17 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		85.37%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	22.860s	922.382us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	9.580s	4584.024us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.680s	54.613us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.860s	26.342us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.440s	343.786us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.250s	112.825us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.870s	70.189us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.860s	26.342us	1	1	100.00
	i2c_csr_aliasing	1.250s	112.825us	1	1	100.00

35/41 passed

85.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.820s	30.489us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	3600.233s	0.000us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	192.560s	17947.941us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.840s	50.940us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	38.550s	5026.409us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	93.970s	2517.570us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.820s	573.990us	1	1	100.00
	i2c_host_fifo_fmt_empty	3.820s	3108.604us	1	1	100.00
	i2c_host_fifo_reset_rx	6.230s	2434.021us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	28.630s	9712.332us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	4.780s	806.275us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.170s	226.245us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.130s	543.387us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	181.360s	65777.925us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.450s	9727.106us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	19.030s	5966.659us	1	1	100.00
	i2c_target_intr_smoke	3.860s	1749.118us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.080s	374.338us	1	1	100.00
	i2c_target_fifo_reset_tx	1.020s	180.632us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	9.640s	8463.664us	1	1	100.00
	i2c_target_stress_rd	19.030s	5966.659us	1	1	100.00
	i2c_target_intr_stress_wr	4.090s	8551.505us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.350s	7774.566us	1	1	100.00
target_clock_stretch				0	1	0.00
	i2c_target_stretch	3.180s	10064.116us	0	1	0.00
bad_address				1	1	100.00
	i2c_target_bad_addr	4.530s	5241.596us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	5.480s	10358.347us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.490s	2638.265us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.250s	102.994us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	192.560s	17947.941us	1	1	100.00
	i2c_host_perf_precise	4.790s	774.273us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	4.780s	806.275us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.770s	95.168us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.980s	2116.401us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.690s	435.714us	1	1	100.00
	i2c_target_nack_txstretch	1.090s	615.365us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	3.900s	603.083us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.530s	456.370us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.760s	14.631us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.850s	16.400us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.600s	38.657us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.600s	38.657us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.680s	54.613us	1	1	100.00
	i2c_csr_rw	0.860s	26.342us	1	1	100.00
	i2c_csr_aliasing	1.250s	112.825us	1	1	100.00
	i2c_same_csr_outstanding	0.880s	23.200us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.680s	54.613us	1	1	100.00
	i2c_csr_rw	0.860s	26.342us	1	1	100.00
	i2c_csr_aliasing	1.250s	112.825us	1	1	100.00
	i2c_same_csr_outstanding	0.880s	23.200us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.580s	54.270us	1	1	100.00
	i2c_sec_cm	1.250s	278.320us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.580s	54.270us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	10.150s	338.436us	1
target_error_intr				1
	i2c_target_unexp_stop	1.350s	402.783us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	0.820s	80.683us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	93558287783477599775309606004522439662760290844544397322637149680166005928488	80	UVM_INFO @ 30488849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	71621518267207918053561415759013319787037756918010714786994236284479520211017	93	UVM_INFO @ 80683061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	i2c_host_stress_all	96208850843800237981148407818863868826876234406574299701803243854979332605999	None
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	63022737572482967802149025932724973371939331922644555024567780780012652224849	84	UVM_INFO @ 543386562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!				1 test run
	i2c_target_stretch	18391988944658934418864724913098018254724626364999146569609679983369946251361	78	UVM_INFO @ 10064116242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'				1 test run
	i2c_target_unexp_stop	95460652556252011974284287362837586495389377402969087364227642857820092134126	79	UVM_ERROR @ 402782780 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A UVM_INFO @ 402782780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	36269758851090204554755042919323701632801532834827663290365210781133661816061	79	UVM_INFO @ 10358346984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	35545512481615765816279700185908909236324602695225070755757594527910733608226	87	UVM_INFO @ 338435861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead				1 test run
	i2c_host_mode_toggle	61128018320076154358576806964363145163468473869406785170350915682890880602835	87	--> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------