Simulation Results: keymgr

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.58 %
  • code
  • 92.05 %
  • assert
  • 97.49 %
  • func
  • 49.21 %
  • line
  • 98.76 %
  • branch
  • 97.81 %
  • cond
  • 93.48 %
  • toggle
  • 84.13 %
  • FSM
  • 86.05 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 3.790s 335.431us 1 1 100.00
random 1 1 100.00
keymgr_random 3.280s 71.406us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 0.990s 33.402us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.060s 17.411us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 4.790s 191.758us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 5.680s 247.956us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.390s 100.176us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.060s 17.411us 1 1 100.00
keymgr_csr_aliasing 5.680s 247.956us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 8.510s 283.678us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 2.960s 440.072us 1 1 100.00
keymgr_sideload_kmac 2.510s 185.807us 1 1 100.00
keymgr_sideload_aes 2.460s 51.577us 1 1 100.00
keymgr_sideload_otbn 2.560s 79.002us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.880s 96.174us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.480s 141.879us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.280s 211.011us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 36.690s 5469.600us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 2.330s 45.157us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.810s 167.721us 1 1 100.00
stress_all 0 1 0.00
keymgr_stress_all 4.300s 124.253us 0 1 0.00
intr_test 1 1 100.00
keymgr_intr_test 0.880s 18.712us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.710s 38.136us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.660s 85.578us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.660s 85.578us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 0.990s 33.402us 1 1 100.00
keymgr_csr_rw 1.060s 17.411us 1 1 100.00
keymgr_csr_aliasing 5.680s 247.956us 1 1 100.00
keymgr_same_csr_outstanding 1.900s 110.523us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 0.990s 33.402us 1 1 100.00
keymgr_csr_rw 1.060s 17.411us 1 1 100.00
keymgr_csr_aliasing 5.680s 247.956us 1 1 100.00
keymgr_same_csr_outstanding 1.900s 110.523us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 10.770s 4095.095us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 10.770s 4095.095us 1 1 100.00
keymgr_tl_intg_err 4.070s 318.661us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 3.110s 285.202us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 3.110s 285.202us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 3.110s 285.202us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 3.110s 285.202us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 2.890s 333.060us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 10.770s 4095.095us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 10.770s 4095.095us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 4.070s 318.661us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 3.110s 285.202us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 8.510s 283.678us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 3.280s 71.406us 1 1 100.00
keymgr_csr_rw 1.060s 17.411us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 3.280s 71.406us 1 1 100.00
keymgr_csr_rw 1.060s 17.411us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 3.280s 71.406us 1 1 100.00
keymgr_csr_rw 1.060s 17.411us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.480s 141.879us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.330s 45.157us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.330s 45.157us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 3.280s 71.406us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.420s 922.342us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 10.770s 4095.095us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 10.770s 4095.095us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 10.770s 4095.095us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 3.790s 120.939us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.480s 141.879us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 10.770s 4095.095us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 10.770s 4095.095us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 10.770s 4095.095us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.790s 120.939us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.790s 120.939us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 10.770s 4095.095us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.790s 120.939us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 10.770s 4095.095us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 3.790s 120.939us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 6.400s 794.214us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StDisabled for Attestation Aes 1 test run
keymgr_stress_all 45692928214215700502871626571045005376233810799573315624868710804757108814003 656
UVM_INFO @ 124253178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 113687394187670664516910412112959542229527960020953001873128598034759938915514 351
UVM_INFO @ 794213782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---