Simulation Results: lc_ctrl/volatile_unlock_disabled

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.90 %
  • code
  • 83.59 %
  • assert
  • 94.97 %
  • func
  • 94.13 %
  • line
  • 97.11 %
  • branch
  • 93.70 %
  • cond
  • 78.80 %
  • toggle
  • 83.83 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.150s 29.902us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.390s 76.680us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.940s 40.847us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.410s 356.441us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.360s 157.616us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.150s 21.305us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.940s 40.847us 1 1 100.00
lc_ctrl_csr_aliasing 1.360s 157.616us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.510s 94.879us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.060s 477.230us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.030s 41.952us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.010s 82.084us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.320s 238.814us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.090s 219.049us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 9.320s 238.814us 1 1 100.00
lc_ctrl_prog_failure 2.010s 82.084us 1 1 100.00
lc_ctrl_errors 4.090s 219.049us 1 1 100.00
lc_ctrl_security_escalation 7.310s 2403.046us 1 1 100.00
lc_ctrl_jtag_state_failure 41.910s 16689.942us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.860s 373.330us 1 1 100.00
lc_ctrl_jtag_errors 25.980s 5918.139us 0 1 0.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 7.000s 2596.586us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.770s 338.154us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.860s 373.330us 1 1 100.00
lc_ctrl_jtag_errors 25.980s 5918.139us 0 1 0.00
lc_ctrl_jtag_access 4.850s 613.621us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 16.760s 824.749us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.930s 957.894us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.100s 465.958us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.860s 474.007us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.890s 926.368us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.160s 108.178us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.750s 504.057us 1 1 100.00
lc_ctrl_jtag_alert_test 0.960s 108.650us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.940s 142.500us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.950s 87.855us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 32.190s 8301.169us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.230s 14.957us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.930s 121.389us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.930s 121.389us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.390s 76.680us 1 1 100.00
lc_ctrl_csr_rw 0.940s 40.847us 1 1 100.00
lc_ctrl_csr_aliasing 1.360s 157.616us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.380s 85.067us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.390s 76.680us 1 1 100.00
lc_ctrl_csr_rw 0.940s 40.847us 1 1 100.00
lc_ctrl_csr_aliasing 1.360s 157.616us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.380s 85.067us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.890s 407.162us 1 1 100.00
lc_ctrl_tl_intg_err 1.360s 67.536us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.360s 67.536us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.060s 477.230us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.320s 238.814us 1 1 100.00
lc_ctrl_sec_cm 6.890s 407.162us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.320s 238.814us 1 1 100.00
lc_ctrl_sec_cm 6.890s 407.162us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.320s 238.814us 1 1 100.00
lc_ctrl_sec_cm 6.890s 407.162us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.320s 238.814us 1 1 100.00
lc_ctrl_sec_cm 6.890s 407.162us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.320s 238.814us 1 1 100.00
lc_ctrl_sec_cm 6.890s 407.162us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.320s 238.814us 1 1 100.00
lc_ctrl_sec_cm 6.890s 407.162us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.320s 238.814us 1 1 100.00
lc_ctrl_sec_cm 6.890s 407.162us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.320s 238.814us 1 1 100.00
lc_ctrl_sec_cm 6.890s 407.162us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.310s 2403.046us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.510s 94.879us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.770s 338.154us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.990s 465.279us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.990s 465.279us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.680s 929.236us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.520s 555.108us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.520s 555.108us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 11.990s 4529.151us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_jtag_errors 49543179145250667921687285455534865128027385472881010762816559024222524970143 1441
UVM_INFO @ 5918138858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 26772054288237213114061285338894064072213942010961304913544082467020292728517 1363
UVM_INFO @ 4529151286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---