Simulation Results: lc_ctrl/volatile_unlock_enabled

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.60 %
  • code
  • 84.43 %
  • assert
  • 94.13 %
  • func
  • 93.24 %
  • line
  • 97.22 %
  • branch
  • 93.66 %
  • cond
  • 79.41 %
  • toggle
  • 87.38 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.060s 68.990us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.950s 58.518us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.830s 13.668us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.990s 25.900us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 91.868us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.030s 97.364us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.830s 13.668us 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 91.868us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 6.120s 385.486us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.640s 1284.928us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.910s 13.526us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.550s 60.010us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.580s 238.355us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.840s 505.666us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.580s 238.355us 1 1 100.00
lc_ctrl_prog_failure 1.550s 60.010us 1 1 100.00
lc_ctrl_errors 5.840s 505.666us 1 1 100.00
lc_ctrl_security_escalation 4.100s 297.727us 1 1 100.00
lc_ctrl_jtag_state_failure 34.090s 5328.314us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.390s 5631.308us 1 1 100.00
lc_ctrl_jtag_errors 32.210s 8160.575us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.060s 591.087us 1 1 100.00
lc_ctrl_jtag_state_post_trans 18.880s 853.459us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.390s 5631.308us 1 1 100.00
lc_ctrl_jtag_errors 32.210s 8160.575us 1 1 100.00
lc_ctrl_jtag_access 4.340s 587.577us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 19.560s 4137.825us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.360s 164.152us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.780s 257.152us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.770s 1403.359us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 17.410s 4172.581us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.110s 15.520us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.410s 296.809us 1 1 100.00
lc_ctrl_jtag_alert_test 0.800s 89.657us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.240s 3661.944us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.910s 71.393us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 63.400s 3362.561us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.960s 31.469us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.030s 610.283us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.030s 610.283us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.950s 58.518us 1 1 100.00
lc_ctrl_csr_rw 0.830s 13.668us 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 91.868us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.980s 16.830us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.950s 58.518us 1 1 100.00
lc_ctrl_csr_rw 0.830s 13.668us 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 91.868us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.980s 16.830us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.630s 501.380us 1 1 100.00
lc_ctrl_tl_intg_err 1.470s 1004.445us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.470s 1004.445us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.640s 1284.928us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.580s 238.355us 1 1 100.00
lc_ctrl_sec_cm 5.630s 501.380us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.580s 238.355us 1 1 100.00
lc_ctrl_sec_cm 5.630s 501.380us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.580s 238.355us 1 1 100.00
lc_ctrl_sec_cm 5.630s 501.380us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.580s 238.355us 1 1 100.00
lc_ctrl_sec_cm 5.630s 501.380us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.580s 238.355us 1 1 100.00
lc_ctrl_sec_cm 5.630s 501.380us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.580s 238.355us 1 1 100.00
lc_ctrl_sec_cm 5.630s 501.380us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.580s 238.355us 1 1 100.00
lc_ctrl_sec_cm 5.630s 501.380us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.580s 238.355us 1 1 100.00
lc_ctrl_sec_cm 5.630s 501.380us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.100s 297.727us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 6.120s 385.486us 1 1 100.00
lc_ctrl_jtag_state_post_trans 18.880s 853.459us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.930s 1424.885us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.930s 1424.885us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.660s 366.662us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.660s 2968.819us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.660s 2968.819us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 39.880s 59657.621us 1 1 100.00