Simulation Results: otbn

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.07 %
  • code
  • 81.85 %
  • assert
  • 90.04 %
  • func
  • 98.31 %
  • block
  • 97.72 %
  • line
  • 97.92 %
  • branch
  • 81.81 %
  • toggle
  • 81.46 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 40.690us 1 1 100.00
single_binary 1 1 100.00
otbn_single 15.000s 209.108us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 21.000s 39.190us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 17.000s 25.231us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 24.000s 305.500us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 22.000s 29.596us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 22.000s 119.443us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 17.000s 25.231us 1 1 100.00
otbn_csr_aliasing 22.000s 29.596us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 68.000s 7058.340us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 30.000s 5025.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 47.000s 627.403us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 94.000s 485.308us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 15.000s 409.163us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 35.000s 141.568us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 24.000s 175.673us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 9.000s 18.558us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 14.000s 65.752us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 24.000s 38.998us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 7.000s 23.912us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 8.000s 156.134us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 8.000s 156.134us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 21.000s 39.190us 1 1 100.00
otbn_csr_rw 17.000s 25.231us 1 1 100.00
otbn_csr_aliasing 22.000s 29.596us 1 1 100.00
otbn_same_csr_outstanding 5.000s 29.099us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 21.000s 39.190us 1 1 100.00
otbn_csr_rw 17.000s 25.231us 1 1 100.00
otbn_csr_aliasing 22.000s 29.596us 1 1 100.00
otbn_same_csr_outstanding 5.000s 29.099us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 11.000s 83.405us 1 1 100.00
otbn_dmem_err 20.000s 53.704us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 26.000s 232.758us 1 1 100.00
otbn_controller_ispr_rdata_err 27.000s 210.237us 1 1 100.00
otbn_mac_bignum_acc_err 10.000s 53.406us 1 1 100.00
otbn_urnd_err 5.000s 35.023us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 10.000s 90.157us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 41.311us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 15.449us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 156.000s 2953.674us 1 1 100.00
otbn_tl_intg_err 67.000s 493.828us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 44.000s 653.980us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 156.000s 2953.674us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 156.000s 2953.674us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 40.690us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 20.000s 53.704us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 11.000s 83.405us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 67.000s 493.828us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 24.000s 175.673us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 83.405us 1 1 100.00
otbn_dmem_err 20.000s 53.704us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 18.558us 1 1 100.00
otbn_illegal_mem_acc 10.000s 90.157us 1 1 100.00
otbn_sec_cm 156.000s 2953.674us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 156.000s 2953.674us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 15.000s 209.108us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 83.405us 1 1 100.00
otbn_dmem_err 20.000s 53.704us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 18.558us 1 1 100.00
otbn_illegal_mem_acc 10.000s 90.157us 1 1 100.00
otbn_sec_cm 156.000s 2953.674us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 156.000s 2953.674us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 24.000s 175.673us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 83.405us 1 1 100.00
otbn_dmem_err 20.000s 53.704us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 18.558us 1 1 100.00
otbn_illegal_mem_acc 10.000s 90.157us 1 1 100.00
otbn_sec_cm 156.000s 2953.674us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 156.000s 2953.674us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 15.000s 209.108us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 18.000s 42.596us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 50.660us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 26.000s 645.621us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 26.000s 645.621us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 10.000s 20.588us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 156.000s 2953.674us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 156.000s 2953.674us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 10.000s 291.078us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 156.000s 2953.674us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 156.000s 2953.674us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 14.000s 35.852us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 14.000s 35.852us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 9.000s 82.072us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 15.000s 209.108us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 15.000s 209.108us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 15.000s 209.108us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 15.000s 409.163us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 15.000s 209.108us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 15.000s 209.108us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 10.000s 53.368us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 15.000s 209.108us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 156.000s 2953.674us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 18.000s 48.351us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 21.868us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_stress_all_with_rand_reset 57343077692721805185162725863196133688027881878432007766291653561239873896991 162
UVM_INFO @ 48351448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---