Simulation Results: pwrmgr

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.78 %
  • code
  • 97.39 %
  • assert
  • 98.43 %
  • func
  • 97.53 %
  • line
  • 99.09 %
  • branch
  • 96.18 %
  • cond
  • 96.04 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.730s 24.444us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.730s 42.748us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.690s 17.666us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.680s 190.304us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.050s 48.194us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.740s 60.634us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.690s 17.666us 1 1 100.00
pwrmgr_csr_aliasing 1.050s 48.194us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.580s 49.075us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.580s 49.075us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.660s 20.274us 1 1 100.00
pwrmgr_lowpower_invalid 0.620s 81.803us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.650s 41.723us 1 1 100.00
pwrmgr_reset_invalid 0.720s 101.675us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.650s 41.723us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.140s 290.329us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.770s 83.390us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.620s 19.147us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.860s 1779.732us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.600s 18.566us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.510s 153.836us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.510s 153.836us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.730s 42.748us 1 1 100.00
pwrmgr_csr_rw 0.690s 17.666us 1 1 100.00
pwrmgr_csr_aliasing 1.050s 48.194us 1 1 100.00
pwrmgr_same_csr_outstanding 0.690s 34.555us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.730s 42.748us 1 1 100.00
pwrmgr_csr_rw 0.690s 17.666us 1 1 100.00
pwrmgr_csr_aliasing 1.050s 48.194us 1 1 100.00
pwrmgr_same_csr_outstanding 0.690s 34.555us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.980s 112.883us 1 1 100.00
pwrmgr_sec_cm 0.850s 450.416us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 0.850s 450.416us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 0.850s 450.416us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.980s 112.883us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.540s 2671.577us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 1.140s 290.329us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.610s 913.790us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.750s 83.159us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.600s 38.276us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 0.850s 450.416us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 0.850s 450.416us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 0.850s 450.416us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.630s 24.975us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.640s 39.831us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.960s 286.785us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.690s 17.666us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.690s 17.666us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.680s 101.541us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 5.290s 2326.496us 1 1 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 100904151290730701864010238801378661095412836109056784534080310838598313316311 79
UVM_ERROR @ 101540839 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 101540839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---