Simulation Results: rom_ctrl/32kb

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.50 %
  • code
  • 96.65 %
  • assert
  • 97.39 %
  • func
  • 95.47 %
  • line
  • 99.19 %
  • branch
  • 98.54 %
  • cond
  • 97.03 %
  • toggle
  • 95.18 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.660s 413.346us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.070s 302.778us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.530s 601.930us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.200s 169.143us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.660s 632.152us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.620s 1050.754us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.530s 601.930us 1 1 100.00
rom_ctrl_csr_aliasing 3.660s 632.152us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.830s 415.542us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.470s 127.965us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 4.280s 396.596us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 12.590s 768.593us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.240s 2811.147us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.550s 126.019us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.780s 288.598us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.780s 288.598us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.070s 302.778us 1 1 100.00
rom_ctrl_csr_rw 3.530s 601.930us 1 1 100.00
rom_ctrl_csr_aliasing 3.660s 632.152us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.780s 516.362us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.070s 302.778us 1 1 100.00
rom_ctrl_csr_rw 3.530s 601.930us 1 1 100.00
rom_ctrl_csr_aliasing 3.660s 632.152us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.780s 516.362us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.850s 31971.606us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 19.500s 3176.794us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 103.690s 1186.721us 1 1 100.00
rom_ctrl_tl_intg_err 23.690s 243.121us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 103.690s 1186.721us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 103.690s 1186.721us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.850s 31971.606us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.850s 31971.606us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.850s 31971.606us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.850s 31971.606us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.850s 31971.606us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 103.690s 1186.721us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 103.690s 1186.721us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.660s 413.346us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.660s 413.346us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.660s 413.346us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 23.690s 243.121us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.850s 31971.606us 1 1 100.00
rom_ctrl_kmac_err_chk 7.240s 2811.147us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.850s 31971.606us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.850s 31971.606us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.850s 31971.606us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 19.500s 3176.794us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 103.690s 1186.721us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 14.360s 1707.296us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 64090468947693812079103936449479524442083444898085199674347701552453835084371 79
UVM_INFO @ 396596120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---