Simulation Results: rom_ctrl/64kb

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.29 %
  • code
  • 97.01 %
  • assert
  • 97.24 %
  • func
  • 97.61 %
  • line
  • 99.33 %
  • branch
  • 98.91 %
  • cond
  • 97.92 %
  • toggle
  • 95.57 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.500s 771.328us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.060s 207.217us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 8.600s 3990.892us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.070s 699.249us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.200s 210.521us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.410s 221.226us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 8.600s 3990.892us 1 1 100.00
rom_ctrl_csr_aliasing 6.200s 210.521us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.860s 210.601us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.760s 1308.978us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 6.240s 1836.660us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 26.380s 4909.678us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 11.890s 723.924us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.290s 212.188us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.000s 756.245us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.000s 756.245us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.060s 207.217us 1 1 100.00
rom_ctrl_csr_rw 8.600s 3990.892us 1 1 100.00
rom_ctrl_csr_aliasing 6.200s 210.521us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.010s 292.629us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.060s 207.217us 1 1 100.00
rom_ctrl_csr_rw 8.600s 3990.892us 1 1 100.00
rom_ctrl_csr_aliasing 6.200s 210.521us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.010s 292.629us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 141.380s 16969.939us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.780s 1064.685us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 246.310s 2474.687us 1 1 100.00
rom_ctrl_tl_intg_err 96.880s 747.062us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 246.310s 2474.687us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 246.310s 2474.687us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 141.380s 16969.939us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 141.380s 16969.939us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 141.380s 16969.939us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 141.380s 16969.939us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 141.380s 16969.939us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 246.310s 2474.687us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 246.310s 2474.687us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.500s 771.328us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.500s 771.328us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.500s 771.328us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 96.880s 747.062us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 141.380s 16969.939us 1 1 100.00
rom_ctrl_kmac_err_chk 11.890s 723.924us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 141.380s 16969.939us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 141.380s 16969.939us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 141.380s 16969.939us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.780s 1064.685us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 246.310s 2474.687us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 30.390s 8300.364us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 39221437589721934676034499743868076460887348587790825347785704682880275100960 79
UVM_INFO @ 1836660291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---