Simulation Results: rstmgr

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.42 %
  • code
  • 99.33 %
  • assert
  • 98.93 %
  • func
  • 97.01 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.47 %
  • toggle
  • 99.50 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.210s 265.870us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.830s 143.817us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.740s 60.276us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.350s 1264.578us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.580s 233.068us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.090s 206.116us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.740s 60.276us 1 1 100.00
rstmgr_csr_aliasing 1.580s 233.068us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.090s 194.163us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.670s 182.398us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.240s 281.332us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.140s 1044.839us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.140s 1044.839us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.140s 1044.839us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.140s 1044.839us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 24.830s 8486.469us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.910s 112.327us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.560s 495.878us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.560s 495.878us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.830s 143.817us 1 1 100.00
rstmgr_csr_rw 0.740s 60.276us 1 1 100.00
rstmgr_csr_aliasing 1.580s 233.068us 1 1 100.00
rstmgr_same_csr_outstanding 1.450s 164.774us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.830s 143.817us 1 1 100.00
rstmgr_csr_rw 0.740s 60.276us 1 1 100.00
rstmgr_csr_aliasing 1.580s 233.068us 1 1 100.00
rstmgr_same_csr_outstanding 1.450s 164.774us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 17.610s 17184.636us 1 1 100.00
rstmgr_tl_intg_err 2.110s 832.445us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 17.610s 17184.636us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 17.610s 17184.636us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.110s 832.445us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.000s 189.357us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 7.310s 2796.089us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.390s 302.040us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 17.610s 17184.636us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.740s 60.276us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.740s 60.276us 1 1 100.00