Simulation Results: spi_device/1r1w

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.90 %
  • code
  • 90.58 %
  • assert
  • 95.15 %
  • func
  • 59.97 %
  • line
  • 98.84 %
  • branch
  • 98.13 %
  • cond
  • 95.84 %
  • toggle
  • 70.75 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 24.600s 6126.992us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.460s 53.876us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.260s 47.820us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 8.180s 270.256us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.830s 2111.338us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.020s 153.864us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.260s 47.820us 1 1 100.00
spi_device_csr_aliasing 5.830s 2111.338us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.930s 13.069us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.240s 117.137us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.850s 43.848us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.780s 1.678us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.770s 7.835us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.350s 100.032us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.350s 100.032us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 10.120s 22415.041us 1 1 100.00
spi_device_tpm_sts_read 1.020s 576.623us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 0.700s 15.065us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 2.370s 452.542us 1 1 100.00
spi_device_flash_all 182.690s 251387.664us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.880s 216.648us 1 1 100.00
spi_device_flash_all 182.690s 251387.664us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.880s 216.648us 1 1 100.00
spi_device_flash_all 182.690s 251387.664us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 182.690s 251387.664us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.800s 1058.879us 1 1 100.00
spi_device_flash_all 182.690s 251387.664us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.800s 1058.879us 1 1 100.00
spi_device_flash_all 182.690s 251387.664us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.800s 1058.879us 1 1 100.00
spi_device_flash_all 182.690s 251387.664us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.800s 1058.879us 1 1 100.00
spi_device_flash_all 182.690s 251387.664us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.800s 1058.879us 1 1 100.00
spi_device_flash_all 182.690s 251387.664us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.760s 3584.990us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 2.130s 389.189us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 2.130s 389.189us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 2.130s 389.189us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 16.800s 2632.721us 1 1 100.00
spi_device_read_buffer_direct 3.100s 755.782us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 2.130s 389.189us 1 1 100.00
spi_device_flash_all 182.690s 251387.664us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 182.690s 251387.664us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 182.690s 251387.664us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 5.680s 838.819us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 5.680s 838.819us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 5.770s 1758.389us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 24.600s 6126.992us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 214.120s 131963.171us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 0.870s 219.362us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.780s 142.956us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.700s 70.239us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.500s 70.558us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.500s 70.558us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.460s 53.876us 1 1 100.00
spi_device_csr_rw 1.260s 47.820us 1 1 100.00
spi_device_csr_aliasing 5.830s 2111.338us 1 1 100.00
spi_device_same_csr_outstanding 2.290s 246.357us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.460s 53.876us 1 1 100.00
spi_device_csr_rw 1.260s 47.820us 1 1 100.00
spi_device_csr_aliasing 5.830s 2111.338us 1 1 100.00
spi_device_same_csr_outstanding 2.290s 246.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.060s 216.103us 1 1 100.00
spi_device_tl_intg_err 5.890s 1397.062us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.890s 1397.062us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 29051523887699267813240415142536913696736782202126519588283657239764555781261 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1157171 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1157171 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[911])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 24862616123423889962646588643174440291316984933374892635654410191086259443675 76
UVM_ERROR @ 5265087 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf224fe [111100100010010011111110] vs 0x0 [0])
UVM_ERROR @ 5286087 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x47b257 [10001111011001001010111] vs 0x0 [0])
UVM_ERROR @ 5351087 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x93508f [100100110101000010001111] vs 0x0 [0])
UVM_ERROR @ 5380087 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x35aab3 [1101011010101010110011] vs 0x0 [0])