Simulation Results: spi_host

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.17 %
  • code
  • 91.25 %
  • assert
  • 96.60 %
  • func
  • 88.66 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 72.90 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 17.000s 2549.966us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 160.473us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 44.053us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 69.803us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 17.887us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 24.912us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 44.053us 1 1 100.00
spi_host_csr_aliasing 2.000s 17.887us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 14.731us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 24.810us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 62.416us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 7.000s 420.882us 1 1 100.00
spi_host_error_cmd 1.000s 20.561us 1 1 100.00
spi_host_event 20.000s 4628.561us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 4.000s 98.741us 1 1 100.00
speed 1 1 100.00
spi_host_speed 4.000s 98.741us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 4.000s 98.741us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 164.000s 25631.725us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 2.000s 149.689us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 30.208us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 4.000s 98.741us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 4.000s 98.741us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 17.000s 2549.966us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 17.000s 2549.966us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 19.000s 1295.902us 1 1 100.00
spien 1 1 100.00
spi_host_spien 4.000s 476.657us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 155.000s 17898.474us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 236.816us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 7.000s 420.882us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 33.302us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 2.000s 18.496us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 726.250us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 726.250us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 160.473us 1 1 100.00
spi_host_csr_rw 1.000s 44.053us 1 1 100.00
spi_host_csr_aliasing 2.000s 17.887us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 20.834us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 160.473us 1 1 100.00
spi_host_csr_rw 1.000s 44.053us 1 1 100.00
spi_host_csr_aliasing 2.000s 17.887us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 20.834us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 98.687us 1 1 100.00
spi_host_sec_cm 2.000s 108.241us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 98.687us 1 1 100.00