Simulation Results: sram_ctrl/main

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.38 %
  • code
  • 95.57 %
  • assert
  • 97.96 %
  • func
  • 92.60 %
  • block
  • 95.90 %
  • line
  • 96.68 %
  • branch
  • 93.85 %
  • toggle
  • 91.74 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 793.890us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 41.789us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 53.170us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 189.486us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 27.024us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 735.314us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 53.170us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 27.024us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 99.000s 3085.741us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 41.000s 3755.497us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 35.000s 36401.301us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 131.000s 5189.831us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 151.000s 18231.336us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 32.000s 8289.311us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 19.000s 13511.259us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 11.000s 2600.968us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 1540.169us 1 1 100.00
sram_ctrl_partial_access_b2b 138.000s 4926.356us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 1119.368us 0 1 0.00
sram_ctrl_throughput_w_partial_write 4.000s 4401.771us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 718.767us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 1525.732us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 1424.720us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 113.000s 40712.061us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 26.143us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 270.338us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 270.338us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 41.789us 1 1 100.00
sram_ctrl_csr_rw 1.000s 53.170us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 27.024us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 86.092us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 41.789us 1 1 100.00
sram_ctrl_csr_rw 1.000s 53.170us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 27.024us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 86.092us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.000s 7276.601us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 1449.721us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 437.976us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 1449.721us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 437.976us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 1525.732us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 1525.732us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 53.170us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 11.000s 2600.968us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 11.000s 2600.968us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 11.000s 2600.968us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 19.000s 13511.259us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 706.607us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.000s 7276.601us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 686.959us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 793.890us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 793.890us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 11.000s 2600.968us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 1449.721us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 19.000s 13511.259us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 1449.721us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1449.721us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 793.890us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1449.721us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 15.000s 926.825us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 44833508003672064470565975925350293145146315850370583479606732242993374806007 86
UVM_INFO @ 1119367619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 89222907390966506403964279655289349727135509363913734944127268612378902716621 86
UVM_INFO @ 4401770714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 71059435200839439081476768350138234474375589821132878360085177909783652339756 86
UVM_INFO @ 718767295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---