| V1 |
|
100.00% |
| V2 |
|
94.44% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| sysrst_ctrl_smoke | 4.710s | 2111.518us | 1 | 1 | 100.00 | |
| input_output_inverted | 1 | 1 | 100.00 | |||
| sysrst_ctrl_in_out_inverted | 1.740s | 2470.766us | 1 | 1 | 100.00 | |
| combo_detect_ec_rst | 1 | 1 | 100.00 | |||
| sysrst_ctrl_combo_detect_ec_rst | 4.230s | 2195.304us | 1 | 1 | 100.00 | |
| combo_detect_ec_rst_with_pre_cond | 1 | 1 | 100.00 | |||
| sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 2.500s | 2380.183us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_hw_reset | 7.690s | 4034.761us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_rw | 2.440s | 2084.700us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_bit_bash | 146.870s | 75931.694us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_aliasing | 7.510s | 2841.438us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_mem_rw_with_rand_reset | 5.030s | 2078.671us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| sysrst_ctrl_csr_rw | 2.440s | 2084.700us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_aliasing | 7.510s | 2841.438us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| combo_detect | 1 | 1 | 100.00 | |||
| sysrst_ctrl_combo_detect | 23.270s | 55187.363us | 1 | 1 | 100.00 | |
| combo_detect_with_pre_cond | 0 | 1 | 0.00 | |||
| sysrst_ctrl_combo_detect_with_pre_cond | 104.320s | 132429.585us | 0 | 1 | 0.00 | |
| auto_block_key_outputs | 1 | 1 | 100.00 | |||
| sysrst_ctrl_auto_blk_key_output | 2.300s | 3516.190us | 1 | 1 | 100.00 | |
| keyboard_input_triggered_interrupt | 1 | 1 | 100.00 | |||
| sysrst_ctrl_edge_detect | 2.510s | 3277.114us | 1 | 1 | 100.00 | |
| pin_output_keyboard_inversion_control | 1 | 1 | 100.00 | |||
| sysrst_ctrl_pin_override_test | 1.960s | 2530.674us | 1 | 1 | 100.00 | |
| pin_input_value_accessibility | 1 | 1 | 100.00 | |||
| sysrst_ctrl_pin_access_test | 0.830s | 2146.535us | 1 | 1 | 100.00 | |
| ec_power_on_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_ec_pwr_on_rst | 7.560s | 3802.016us | 1 | 1 | 100.00 | |
| flash_write_protect_output | 1 | 1 | 100.00 | |||
| sysrst_ctrl_flash_wr_prot_out | 1.650s | 2630.366us | 1 | 1 | 100.00 | |
| ultra_low_power_test | 1 | 1 | 100.00 | |||
| sysrst_ctrl_ultra_low_pwr | 4.850s | 4432.177us | 1 | 1 | 100.00 | |
| sysrst_ctrl_feature_disable | 1 | 1 | 100.00 | |||
| sysrst_ctrl_feature_disable | 17.700s | 38637.440us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| sysrst_ctrl_stress_all | 17.520s | 15018.611us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| sysrst_ctrl_alert_test | 0.990s | 2085.006us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| sysrst_ctrl_intr_test | 4.370s | 2014.154us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| sysrst_ctrl_tl_errors | 1.950s | 3317.670us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| sysrst_ctrl_tl_errors | 1.950s | 3317.670us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| sysrst_ctrl_csr_hw_reset | 7.690s | 4034.761us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_rw | 2.440s | 2084.700us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_aliasing | 7.510s | 2841.438us | 1 | 1 | 100.00 | |
| sysrst_ctrl_same_csr_outstanding | 3.890s | 10087.410us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| sysrst_ctrl_csr_hw_reset | 7.690s | 4034.761us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_rw | 2.440s | 2084.700us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_aliasing | 7.510s | 2841.438us | 1 | 1 | 100.00 | |
| sysrst_ctrl_same_csr_outstanding | 3.890s | 10087.410us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| sysrst_ctrl_sec_cm | 7.450s | 22125.912us | 1 | 1 | 100.00 | |
| sysrst_ctrl_tl_intg_err | 20.570s | 42502.432us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| sysrst_ctrl_tl_intg_err | 20.570s | 42502.432us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_stress_all_with_rand_reset | 4.680s | 4475.840us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) | 1 test run | |||
| sysrst_ctrl_combo_detect_with_pre_cond | 98170627515208813695253918409935818550019429555600741969845516130731858931862 | 726 |
UVM_INFO @ 85183328743 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 85203328743 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 95293266988 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2e
UVM_INFO @ 95293711428 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x22
|
|