Simulation Results: uart

 
30/06/2026 15:30:29 DVSim: v1.49.11 sha: 9a3aadf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.02 %
  • code
  • 96.77 %
  • assert
  • 98.56 %
  • func
  • 50.73 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.90 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.540s 483.114us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.700s 22.687us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.610s 78.507us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.870s 459.864us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.950s 42.068us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.960s 18.189us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.610s 78.507us 1 1 100.00
uart_csr_aliasing 0.950s 42.068us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 12.480s 12525.603us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.540s 483.114us 1 1 100.00
uart_tx_rx 12.480s 12525.603us 1 1 100.00
parity_error 2 2 100.00
uart_intr 57.340s 74115.495us 1 1 100.00
uart_rx_parity_err 40.290s 268058.152us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 12.480s 12525.603us 1 1 100.00
uart_intr 57.340s 74115.495us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 26.720s 35347.913us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 41.230s 58249.602us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 19.980s 87302.637us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 57.340s 74115.495us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 57.340s 74115.495us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 57.340s 74115.495us 1 1 100.00
perf 1 1 100.00
uart_perf 376.480s 14195.089us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.060s 6589.143us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.060s 6589.143us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.800s 4732.559us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 4.610s 3917.075us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.300s 1821.292us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 11.280s 2969.077us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 362.320s 165791.759us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 22.980s 139986.541us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.660s 12.609us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.660s 14.618us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.850s 739.940us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.850s 739.940us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.700s 22.687us 1 1 100.00
uart_csr_rw 0.610s 78.507us 1 1 100.00
uart_csr_aliasing 0.950s 42.068us 1 1 100.00
uart_same_csr_outstanding 0.880s 128.575us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.700s 22.687us 1 1 100.00
uart_csr_rw 0.610s 78.507us 1 1 100.00
uart_csr_aliasing 0.950s 42.068us 1 1 100.00
uart_same_csr_outstanding 0.880s 128.575us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.210s 244.563us 1 1 100.00
uart_tl_intg_err 0.990s 194.923us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.990s 194.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 7.150s 723.387us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 16345682275427571714993314952325956631121347854455409912829477778123597181540 74
UVM_ERROR @ 661238687 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 661278687 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 250 [0xfa]) reg name: uart_reg_block.rdata
UVM_ERROR @ 666278687 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 666278687 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0