Simulation Results: adc_ctrl

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.76 %
  • code
  • 92.25 %
  • assert
  • 91.90 %
  • func
  • 13.12 %
  • line
  • 98.00 %
  • branch
  • 96.23 %
  • cond
  • 86.19 %
  • toggle
  • 99.76 %
  • FSM
  • 81.08 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 2.720s 5814.437us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.410s 1274.920us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.880s 594.276us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 2.630s 1098.144us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.770s 461.952us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.040s 407.988us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.880s 594.276us 1 1 100.00
adc_ctrl_csr_aliasing 1.770s 461.952us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.170s 412.038us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.420s 521.785us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.700s 469.250us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.080s 350.131us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.870s 454.988us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.660s 379.279us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.670s 372.241us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.720s 528.070us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 2.440s 5006.456us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 16.120s 28537.165us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 14.550s 134589.750us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 1.080s 753.643us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.840s 391.318us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.090s 372.178us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.790s 1071.536us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.790s 1071.536us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.410s 1274.920us 1 1 100.00
adc_ctrl_csr_rw 0.880s 594.276us 1 1 100.00
adc_ctrl_csr_aliasing 1.770s 461.952us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.820s 2200.998us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.410s 1274.920us 1 1 100.00
adc_ctrl_csr_rw 0.880s 594.276us 1 1 100.00
adc_ctrl_csr_aliasing 1.770s 461.952us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.820s 2200.998us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 3.520s 8211.832us 1 1 100.00
adc_ctrl_tl_intg_err 7.050s 4255.447us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 7.050s 4255.447us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.410s 717.584us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 41070453475467120958542838378193262308155955574654711135009496825344303065274 386
UVM_INFO @ 412038289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 28101927987272571103683601090519535199359691855079194961481875994486057457690 386
UVM_INFO @ 521785229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 86495769694567141598618010154447057530093790250887980584366225889181055095325 386
UVM_INFO @ 469250319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 86954442577928993945081388876612045231592024669632980623621890567704408697354 386
UVM_INFO @ 350131032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 54250709596681403489034619259028754271570987877475209739944198502039986163150 386
UVM_INFO @ 454988482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 54385939673943939163052425947836721040103707613926346133548461284110786121053 386
UVM_INFO @ 379279083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 75675648236553929701205831723743701902991919470657879850873659936530306431116 386
UVM_INFO @ 528069893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 45430161798202716335569740651951690649247940261702660785152576174151693108352 386
UVM_INFO @ 372240745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 77741384593544584671891173696583716486381168129023779904283605388115485092347 392
UVM_INFO @ 717584002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 96735139438960914231229924778852843689464175520785888441464371810803248171213 387
UVM_INFO @ 753643182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---