Simulation Results: aes/masked

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.92 %
  • code
  • 93.60 %
  • assert
  • 98.09 %
  • func
  • 72.08 %
  • block
  • 94.27 %
  • line
  • 95.96 %
  • branch
  • 87.11 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 57.134us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 154.996us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 94.801us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 75.506us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 2118.448us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 97.661us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 80.262us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 75.506us 1 1 100.00
aes_csr_aliasing 2.000s 97.661us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 154.996us 1 1 100.00
aes_config_error 3.000s 90.972us 1 1 100.00
aes_stress 3.000s 119.211us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 154.996us 1 1 100.00
aes_config_error 3.000s 90.972us 1 1 100.00
aes_stress 3.000s 119.211us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 119.211us 1 1 100.00
aes_b2b 8.000s 354.185us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 119.211us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 154.996us 1 1 100.00
aes_config_error 3.000s 90.972us 1 1 100.00
aes_stress 3.000s 119.211us 1 1 100.00
aes_alert_reset 3.000s 126.346us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 64.135us 1 1 100.00
aes_config_error 3.000s 90.972us 1 1 100.00
aes_alert_reset 3.000s 126.346us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 110.695us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 11.000s 471.559us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 126.346us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 119.211us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 119.211us 1 1 100.00
aes_sideload 2.000s 327.973us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 93.443us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 12.000s 72.197us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 61.860us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 68.341us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 68.341us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 94.801us 1 1 100.00
aes_csr_rw 1.000s 75.506us 1 1 100.00
aes_csr_aliasing 2.000s 97.661us 1 1 100.00
aes_same_csr_outstanding 2.000s 168.400us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 94.801us 1 1 100.00
aes_csr_rw 1.000s 75.506us 1 1 100.00
aes_csr_aliasing 2.000s 97.661us 1 1 100.00
aes_same_csr_outstanding 2.000s 168.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 3.000s 44.621us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 3.000s 288.766us 0 1 0.00
aes_control_fi 2.000s 48.093us 1 1 100.00
aes_cipher_fi 3.000s 71.372us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 87.159us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 87.159us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 87.159us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 87.159us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 1.000s 71.894us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 742.580us 1 1 100.00
aes_tl_intg_err 2.000s 177.173us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 177.173us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 126.346us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 87.159us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 87.159us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 154.996us 1 1 100.00
aes_stress 3.000s 119.211us 1 1 100.00
aes_alert_reset 3.000s 126.346us 1 1 100.00
aes_core_fi 3.000s 163.676us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 90.972us 1 1 100.00
aes_stress 3.000s 119.211us 1 1 100.00
aes_core_fi 3.000s 163.676us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 87.159us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 80.388us 1 1 100.00
aes_stress 3.000s 119.211us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 119.211us 1 1 100.00
aes_sideload 2.000s 327.973us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 80.388us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 80.388us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 80.388us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 80.388us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 80.388us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 119.211us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 119.211us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 288.766us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 288.766us 0 1 0.00
aes_control_fi 2.000s 48.093us 1 1 100.00
aes_cipher_fi 3.000s 71.372us 1 1 100.00
aes_ctr_fi 2.000s 82.157us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 288.766us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 288.766us 0 1 0.00
aes_control_fi 2.000s 48.093us 1 1 100.00
aes_cipher_fi 3.000s 71.372us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 71.372us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 288.766us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 288.766us 0 1 0.00
aes_control_fi 2.000s 48.093us 1 1 100.00
aes_ctr_fi 2.000s 82.157us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 288.766us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 288.766us 0 1 0.00
aes_control_fi 2.000s 48.093us 1 1 100.00
aes_cipher_fi 3.000s 71.372us 1 1 100.00
aes_ctr_fi 2.000s 82.157us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 126.346us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 288.766us 0 1 0.00
aes_control_fi 2.000s 48.093us 1 1 100.00
aes_cipher_fi 3.000s 71.372us 1 1 100.00
aes_ctr_fi 2.000s 82.157us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 288.766us 0 1 0.00
aes_control_fi 2.000s 48.093us 1 1 100.00
aes_cipher_fi 3.000s 71.372us 1 1 100.00
aes_ctr_fi 2.000s 82.157us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 288.766us 0 1 0.00
aes_control_fi 2.000s 48.093us 1 1 100.00
aes_ctr_fi 2.000s 82.157us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 288.766us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 288.766us 0 1 0.00
aes_control_fi 2.000s 48.093us 1 1 100.00
aes_cipher_fi 3.000s 71.372us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 12.000s 466.626us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 105020278459283585570356626221087211268098308456494031721294384785885048458507 11269
UVM_INFO @ 44620560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 6463182254897296203348166319975996691660627990282527062976922767574525531494 15796
UVM_INFO @ 72197361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 13069545342695248083971891059994412357398589685847447200686776680011883827737 15336
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (aes_base_vseq.sv:87) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 45035513104775525739569757853281570346107134857269209318156752216391647570927 464
UVM_INFO @ 466626477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---