Simulation Results: aes/unmasked

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.22 %
  • code
  • 89.73 %
  • assert
  • 97.73 %
  • func
  • 74.19 %
  • block
  • 89.71 %
  • line
  • 91.95 %
  • branch
  • 80.10 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 93.644us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 65.250us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 72.466us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 55.317us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 204.327us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 153.694us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 193.287us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 55.317us 1 1 100.00
aes_csr_aliasing 2.000s 153.694us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 65.250us 1 1 100.00
aes_config_error 1.000s 94.468us 1 1 100.00
aes_stress 2.000s 185.564us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 65.250us 1 1 100.00
aes_config_error 1.000s 94.468us 1 1 100.00
aes_stress 2.000s 185.564us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 185.564us 1 1 100.00
aes_b2b 3.000s 244.433us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 185.564us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 65.250us 1 1 100.00
aes_config_error 1.000s 94.468us 1 1 100.00
aes_stress 2.000s 185.564us 1 1 100.00
aes_alert_reset 1.000s 80.506us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 81.954us 1 1 100.00
aes_config_error 1.000s 94.468us 1 1 100.00
aes_alert_reset 1.000s 80.506us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 260.189us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 2065.383us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 1.000s 80.506us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 185.564us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 185.564us 1 1 100.00
aes_sideload 2.000s 56.612us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 311.644us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 22.000s 1915.247us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 56.002us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 110.356us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 110.356us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 72.466us 1 1 100.00
aes_csr_rw 2.000s 55.317us 1 1 100.00
aes_csr_aliasing 2.000s 153.694us 1 1 100.00
aes_same_csr_outstanding 2.000s 73.106us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 72.466us 1 1 100.00
aes_csr_rw 2.000s 55.317us 1 1 100.00
aes_csr_aliasing 2.000s 153.694us 1 1 100.00
aes_same_csr_outstanding 2.000s 73.106us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 242.081us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 302.217us 0 1 0.00
aes_control_fi 2.000s 58.896us 1 1 100.00
aes_cipher_fi 2.000s 230.933us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 172.724us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 172.724us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 172.724us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 172.724us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 84.506us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 952.005us 1 1 100.00
aes_tl_intg_err 2.000s 182.766us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 182.766us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 1.000s 80.506us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 172.724us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 172.724us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 65.250us 1 1 100.00
aes_stress 2.000s 185.564us 1 1 100.00
aes_alert_reset 1.000s 80.506us 1 1 100.00
aes_core_fi 2.000s 69.745us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 1.000s 94.468us 1 1 100.00
aes_stress 2.000s 185.564us 1 1 100.00
aes_core_fi 2.000s 69.745us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 172.724us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 70.494us 1 1 100.00
aes_stress 2.000s 185.564us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 185.564us 1 1 100.00
aes_sideload 2.000s 56.612us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 70.494us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 70.494us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 70.494us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 70.494us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 70.494us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 185.564us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 185.564us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 302.217us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 302.217us 0 1 0.00
aes_control_fi 2.000s 58.896us 1 1 100.00
aes_cipher_fi 2.000s 230.933us 1 1 100.00
aes_ctr_fi 2.000s 65.165us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 302.217us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 302.217us 0 1 0.00
aes_control_fi 2.000s 58.896us 1 1 100.00
aes_cipher_fi 2.000s 230.933us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 230.933us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 302.217us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 302.217us 0 1 0.00
aes_control_fi 2.000s 58.896us 1 1 100.00
aes_ctr_fi 2.000s 65.165us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 302.217us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 302.217us 0 1 0.00
aes_control_fi 2.000s 58.896us 1 1 100.00
aes_cipher_fi 2.000s 230.933us 1 1 100.00
aes_ctr_fi 2.000s 65.165us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 1.000s 80.506us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 302.217us 0 1 0.00
aes_control_fi 2.000s 58.896us 1 1 100.00
aes_cipher_fi 2.000s 230.933us 1 1 100.00
aes_ctr_fi 2.000s 65.165us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 302.217us 0 1 0.00
aes_control_fi 2.000s 58.896us 1 1 100.00
aes_cipher_fi 2.000s 230.933us 1 1 100.00
aes_ctr_fi 2.000s 65.165us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 302.217us 0 1 0.00
aes_control_fi 2.000s 58.896us 1 1 100.00
aes_ctr_fi 2.000s 65.165us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 302.217us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 302.217us 0 1 0.00
aes_control_fi 2.000s 58.896us 1 1 100.00
aes_cipher_fi 2.000s 230.933us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 26.968us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 33046492515436861315646601459900132432243610342011938627785767257028301345196 4231
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
UVM_FATAL (aes_base_vseq.sv:87) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 22157124681841255771626984571884625913502776421842871407635720436189290099039 109
UVM_INFO @ 26968279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---