Simulation Results: chip

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.55 %
  • code
  • 83.67 %
  • assert
  • 97.49 %
  • func
  • 42.50 %
  • line
  • 94.00 %
  • branch
  • 92.34 %
  • cond
  • 87.68 %
  • toggle
  • 87.20 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
77.62%
V2S
50.00%
V3
65.38%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 143.250s 2932.295us 1 1 100.00
chip_sw_example_rom 72.570s 2804.149us 1 1 100.00
chip_sw_example_manufacturer 134.820s 3096.573us 1 1 100.00
chip_sw_example_concurrency 134.680s 2802.487us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 261.220s 7975.293us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 372.760s 5605.705us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 387.580s 5829.035us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4885.570s 36348.565us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 55.560s 2285.863us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4885.570s 36348.565us 1 1 100.00
chip_csr_rw 372.760s 5605.705us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.340s 219.852us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 286.430s 4650.052us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 286.430s 4650.052us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 286.430s 4650.052us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 359.990s 4407.505us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 359.990s 4407.505us 1 1 100.00
chip_sw_uart_tx_rx_idx1 391.510s 4300.536us 1 1 100.00
chip_sw_uart_tx_rx_idx2 322.650s 4566.290us 1 1 100.00
chip_sw_uart_tx_rx_idx3 342.200s 3863.399us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 334.710s 4020.112us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1109.120s 8538.206us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 260.060s 4027.287us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 227.250s 4469.592us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 227.250s 4469.592us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 0 1 0.00
chip_sw_sleep_pin_mio_dio_val 199.280s 3142.001us 0 1 0.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 267.280s 6216.840us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 219.890s 4754.496us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 767.730s 12606.546us 1 1 100.00
chip_tap_straps_testunlock0 253.830s 4769.546us 1 1 100.00
chip_tap_straps_rma 309.020s 5638.171us 1 1 100.00
chip_tap_straps_prod 83.480s 2348.090us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 440.400s 5929.114us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 440.400s 5929.114us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 532.530s 7523.328us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 962.960s 9962.025us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 359.750s 4213.069us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 552.380s 5452.706us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3909.330s 18560.713us 1 1 100.00
chip_sw_aes_enc_jitter_en 207.010s 3942.270us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 850.160s 8468.525us 1 1 100.00
chip_sw_hmac_enc_jitter_en 161.680s 3003.271us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 773.680s 8943.609us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 193.170s 3613.262us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 358.890s 4524.893us 1 1 100.00
chip_sw_clkmgr_jitter 166.480s 2744.425us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 197.610s 3224.065us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 528.370s 7958.082us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 244.030s 5961.882us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 182.820s 2578.745us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 244.030s 5961.882us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 164.530s 3505.167us 1 1 100.00
chip_sw_aes_smoketest 156.060s 3113.866us 1 1 100.00
chip_sw_aon_timer_smoketest 230.910s 3482.131us 1 1 100.00
chip_sw_clkmgr_smoketest 170.810s 3354.867us 1 1 100.00
chip_sw_csrng_smoketest 138.650s 2891.060us 1 1 100.00
chip_sw_entropy_src_smoketest 1130.820s 8046.321us 1 1 100.00
chip_sw_gpio_smoketest 200.350s 3640.962us 1 1 100.00
chip_sw_hmac_smoketest 204.310s 3750.483us 1 1 100.00
chip_sw_kmac_smoketest 237.660s 3272.023us 1 1 100.00
chip_sw_otbn_smoketest 1047.450s 7857.600us 1 1 100.00
chip_sw_pwrmgr_smoketest 291.650s 5455.982us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 312.890s 6622.313us 1 1 100.00
chip_sw_rv_plic_smoketest 157.780s 2825.686us 1 1 100.00
chip_sw_rv_timer_smoketest 147.080s 3354.281us 1 1 100.00
chip_sw_rstmgr_smoketest 176.940s 3257.793us 1 1 100.00
chip_sw_sram_ctrl_smoketest 154.980s 2865.263us 1 1 100.00
chip_sw_uart_smoketest 186.070s 3530.712us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 120.900s 2866.975us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 263.090s 4472.889us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7957.790s 59841.408us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3001.070s 14512.566us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 25.186s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 1013.810s 15147.726us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 926.790s 14644.825us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6844.150s 53293.181us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7270.950s 55559.955us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 56.750s 2879.282us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 56.750s 2879.282us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4885.570s 36348.565us 1 1 100.00
chip_same_csr_outstanding 2691.620s 27863.134us 1 1 100.00
chip_csr_hw_reset 261.220s 7975.293us 1 1 100.00
chip_csr_rw 372.760s 5605.705us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4885.570s 36348.565us 1 1 100.00
chip_same_csr_outstanding 2691.620s 27863.134us 1 1 100.00
chip_csr_hw_reset 261.220s 7975.293us 1 1 100.00
chip_csr_rw 372.760s 5605.705us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 12.070s 428.809us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.630s 52.754us 1 1 100.00
xbar_smoke_large_delays 39.000s 6387.310us 1 1 100.00
xbar_smoke_slow_rsp 41.820s 4813.462us 1 1 100.00
xbar_random_zero_delays 32.950s 459.861us 1 1 100.00
xbar_random_large_delays 261.880s 43586.095us 1 1 100.00
xbar_random_slow_rsp 263.770s 30840.509us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 34.460s 1228.971us 1 1 100.00
xbar_error_and_unmapped_addr 24.430s 948.461us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 43.740s 1812.375us 1 1 100.00
xbar_error_and_unmapped_addr 24.430s 948.461us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 15.710s 315.860us 1 1 100.00
xbar_access_same_device_slow_rsp 513.630s 62377.117us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 9.240s 345.986us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 60.900s 893.505us 1 1 100.00
xbar_stress_all_with_error 137.410s 6181.536us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 190.790s 1893.604us 1 1 100.00
xbar_stress_all_with_reset_error 195.620s 887.812us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3001.070s 14512.566us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2565.810s 30278.236us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 3258.380s 18692.908us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 43.353s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 11.739s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 7.598s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 8.434s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 10.012s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 46.416s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 22.546s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 47.819s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 21.459s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 9.024s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 165.054s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 121.009s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 51.424s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 36.659s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 38.636s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 21.770s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 18.660s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 21.460s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 21.600s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 20.310s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 19.740s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 19.810s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 21.100s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 18.880s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 18.710s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 18.540s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 18.680s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 19.640s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 19.320s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 18.160s 10.160us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 45.722s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 109.463s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 53.678s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 51.275s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 57.604s 0.000us 0 1 0.00
rom_e2e_keymgr_init 3 3 100.00
rom_e2e_keymgr_init_rom_ext_meas 5862.510s 28675.108us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 5927.980s 27942.797us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 5846.870s 30981.137us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3159.770s 15658.343us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3403.460s 34500.416us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3403.460s 34500.416us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 167.230s 3052.760us 1 1 100.00
chip_sw_aes_enc_jitter_en 207.010s 3942.270us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 158.270s 2468.193us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 184.390s 3243.108us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1211.380s 10526.614us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 206.590s 3107.250us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 322.880s 5239.052us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 386.890s 5800.248us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 436.090s 4233.835us 1 1 100.00
chip_plic_all_irqs_10 231.420s 3366.555us 1 1 100.00
chip_plic_all_irqs_20 340.160s 3907.255us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 197.680s 3515.596us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 935.200s 12389.489us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 219.410s 3425.426us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 165.170s 3058.810us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.135s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 916.950s 7919.909us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 828.600s 6999.817us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 789.500s 7641.731us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8932.330s 256134.827us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 252.250s 4233.805us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 291.650s 5455.982us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 252.250s 4233.805us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 508.050s 8663.196us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 508.050s 8663.196us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 299.200s 7457.478us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 388.600s 4892.521us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 582.050s 6198.846us 1 1 100.00
chip_sw_aes_idle 184.390s 3243.108us 1 1 100.00
chip_sw_hmac_enc_idle 122.930s 2335.147us 1 1 100.00
chip_sw_kmac_idle 179.300s 3175.294us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 299.230s 4928.491us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 259.260s 4632.839us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 231.060s 4272.144us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 243.350s 4769.327us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 721.620s 10383.319us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 388.410s 4094.512us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 374.790s 5033.712us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 417.530s 3755.357us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 383.280s 5298.086us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 378.140s 4658.609us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 351.280s 4367.960us 1 1 100.00
chip_sw_ast_clk_outputs 532.530s 7523.328us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 537.630s 11371.659us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 417.530s 3755.357us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 383.280s 5298.086us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 359.750s 4213.069us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 552.380s 5452.706us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3909.330s 18560.713us 1 1 100.00
chip_sw_aes_enc_jitter_en 207.010s 3942.270us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 850.160s 8468.525us 1 1 100.00
chip_sw_hmac_enc_jitter_en 161.680s 3003.271us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 773.680s 8943.609us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 193.170s 3613.262us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 358.890s 4524.893us 1 1 100.00
chip_sw_clkmgr_jitter 166.480s 2744.425us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 156.530s 3072.925us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 360.570s 4648.775us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 585.920s 6588.669us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4105.880s 25442.482us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 169.110s 3345.651us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 166.580s 3690.288us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1138.020s 11533.781us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 179.860s 3859.281us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 344.540s 5192.461us 1 1 100.00
chip_sw_flash_init_reduced_freq 1301.340s 26290.724us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 14121.660s 168414.569us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 532.530s 7523.328us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 328.840s 4311.377us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 248.900s 3134.891us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 386.890s 5800.248us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 916.950s 7919.909us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1961.200s 24588.038us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 281.610s 4028.842us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 407.990s 6510.176us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 203.610s 3057.780us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 2392.040s 14158.845us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 194.100s 2743.272us 1 1 100.00
chip_sw_edn_entropy_reqs 613.720s 5973.886us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 194.100s 2743.272us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1961.200s 24588.038us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 126.830s 2274.107us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1101.930s 19846.417us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 514.710s 5869.114us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 552.380s 5452.706us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 364.930s 3668.528us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 359.750s 4213.069us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3444.790s 42571.665us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1101.930s 19846.417us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 211.560s 3225.790us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 881.750s 8087.974us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 149.220s 2351.116us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3444.790s 42571.665us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 149.220s 2351.116us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 149.220s 2351.116us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 149.220s 2351.116us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 149.220s 2351.116us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 386.890s 5800.248us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 268.580s 8234.757us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 535.500s 4934.571us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 363.160s 4949.682us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 363.160s 4949.682us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 171.300s 2925.581us 1 1 100.00
chip_sw_hmac_enc_jitter_en 161.680s 3003.271us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 122.930s 2335.147us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 717.260s 5848.811us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1733.730s 12026.732us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 473.340s 5325.223us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 480.680s 5557.872us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 324.990s 4375.479us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 280.890s 3662.417us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 881.750s 8087.974us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 773.680s 8943.609us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1656.190s 13596.198us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1211.380s 10526.614us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 4219.910s 20026.991us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 135.860s 2771.370us 1 1 100.00
chip_sw_kmac_mode_kmac 224.100s 3167.661us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 193.170s 3613.262us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 881.750s 8087.974us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 333.290s 5670.559us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 180.800s 3091.310us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 648.560s 5560.094us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 179.300s 3175.294us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 322.880s 5239.052us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 767.730s 12606.546us 1 1 100.00
chip_tap_straps_rma 309.020s 5638.171us 1 1 100.00
chip_tap_straps_prod 83.480s 2348.090us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 137.200s 2492.016us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 333.290s 5670.559us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 333.290s 5670.559us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 333.290s 5670.559us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1507.140s 12463.383us 1 1 100.00
chip_sw_lc_ctrl_broadcast 20 22 90.91
chip_sw_flash_ctrl_lc_rw_en 149.220s 2351.116us 0 1 0.00
chip_sw_flash_rma_unlocked 3444.790s 42571.665us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 225.460s 3320.309us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 533.020s 7178.099us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 566.820s 7118.870us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 406.350s 5472.563us 0 1 0.00
chip_sw_lc_ctrl_transition 333.290s 5670.559us 1 1 100.00
chip_sw_keymgr_key_derivation 881.750s 8087.974us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 425.690s 9633.499us 1 1 100.00
chip_sw_sram_ctrl_execution_main 533.320s 10325.577us 1 1 100.00
chip_prim_tl_access 268.580s 8234.757us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 537.630s 11371.659us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 388.410s 4094.512us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 374.790s 5033.712us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 417.530s 3755.357us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 383.280s 5298.086us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 378.140s 4658.609us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 351.280s 4367.960us 1 1 100.00
chip_tap_straps_dev 767.730s 12606.546us 1 1 100.00
chip_tap_straps_rma 309.020s 5638.171us 1 1 100.00
chip_tap_straps_prod 83.480s 2348.090us 1 1 100.00
chip_rv_dm_lc_disabled 280.460s 8934.696us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 156.630s 4008.630us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 98.020s 3065.059us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 79.460s 3902.968us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 145.900s 3790.039us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 2015.740s 44832.896us 0 1 0.00
chip_rv_dm_lc_disabled 280.460s 8934.696us 1 1 100.00
chip_sw_lc_walkthrough 1 5 20.00
chip_sw_lc_walkthrough_dev 558.730s 7796.692us 0 1 0.00
chip_sw_lc_walkthrough_prod 685.140s 11815.870us 0 1 0.00
chip_sw_lc_walkthrough_prodend 695.240s 11505.673us 1 1 100.00
chip_sw_lc_walkthrough_rma 337.950s 6679.245us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 2015.740s 44832.896us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 78.420s 2984.284us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 59.740s 1954.564us 1 1 100.00
rom_volatile_raw_unlock 105.411s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3839.520s 16988.310us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3909.330s 18560.713us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 582.050s 6198.846us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 582.050s 6198.846us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 582.050s 6198.846us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 335.160s 4357.295us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 333.290s 5670.559us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1101.930s 19846.417us 1 1 100.00
chip_sw_otbn_mem_scramble 335.160s 4357.295us 1 1 100.00
chip_sw_keymgr_key_derivation 881.750s 8087.974us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 445.910s 5925.250us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 162.460s 3393.791us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1101.930s 19846.417us 1 1 100.00
chip_sw_otbn_mem_scramble 335.160s 4357.295us 1 1 100.00
chip_sw_keymgr_key_derivation 881.750s 8087.974us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 445.910s 5925.250us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 162.460s 3393.791us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 333.290s 5670.559us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 332.250s 4616.244us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 137.200s 2492.016us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 225.460s 3320.309us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 533.020s 7178.099us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 566.820s 7118.870us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 406.350s 5472.563us 0 1 0.00
chip_sw_lc_ctrl_transition 333.290s 5670.559us 1 1 100.00
chip_prim_tl_access 268.580s 8234.757us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 268.580s 8234.757us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 774.050s 6955.779us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 66.070s 1871.659us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1230.820s 25238.902us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 193.020s 7409.712us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 415.850s 7652.194us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 448.640s 8258.477us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1082.830s 21749.400us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 2 2 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 822.410s 13752.487us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 508.050s 8663.196us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 858.500s 10879.583us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 266.970s 5567.015us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 66.070s 1871.659us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 243.130s 4717.814us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 501.680s 8313.340us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 283.750s 7333.762us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 128.260s 3335.992us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 169.170s 5376.636us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 746.270s 9149.519us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1114.140s 12929.384us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1603.780s 28798.109us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 206.630s 3950.383us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 386.890s 5800.248us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 425.690s 9633.499us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 425.690s 9633.499us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1114.140s 12929.384us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 169.170s 5376.636us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 266.970s 5567.015us 1 1 100.00
chip_sw_pwrmgr_smoketest 291.650s 5455.982us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 260.890s 4593.442us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 408.510s 5759.455us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 321.070s 5482.070us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 935.200s 12389.489us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 175.470s 2849.053us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 386.890s 5800.248us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 828.600s 6999.817us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 521.880s 5694.721us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 512.070s 4776.006us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 155.680s 2565.716us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 162.460s 3393.791us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 408.510s 5759.455us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 408.510s 5759.455us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 125.750s 2815.988us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 511.410s 8308.466us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 840.900s 14284.381us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 260.890s 4593.442us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 171.230s 2806.649us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 1424.510s 13229.777us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 309.020s 5638.171us 1 1 100.00
chip_rv_dm_lc_disabled 1 1 100.00
chip_rv_dm_lc_disabled 280.460s 8934.696us 1 1 100.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 436.090s 4233.835us 1 1 100.00
chip_plic_all_irqs_10 231.420s 3366.555us 1 1 100.00
chip_plic_all_irqs_20 340.160s 3907.255us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 144.640s 2435.031us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 196.960s 3272.204us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3001.070s 14512.566us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 244.330s 3553.401us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 193.730s 3348.851us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 201.740s 3527.561us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 204.170s 3593.091us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 445.910s 5925.250us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 358.890s 4524.893us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 332.520s 6978.426us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 329.520s 7754.271us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 533.320s 10325.577us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 386.890s 5800.248us 1 1 100.00
chip_sw_data_integrity_escalation 440.400s 5929.114us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 746.270s 9149.519us 1 1 100.00
chip_sw_sysrst_ctrl_reset 919.480s 22715.243us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 162.800s 2574.255us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 202.690s 3301.021us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 301.680s 5007.952us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 919.480s 22715.243us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 919.480s 22715.243us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2243.790s 20474.346us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2243.790s 20474.346us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 272.860s 6304.993us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3403.460s 34500.416us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 120.200s 3021.183us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 199.450s 3520.631us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 306.690s 4528.741us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 345.730s 4052.496us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 985.790s 9117.220us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5547.970s 31792.012us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1866.780s 12385.438us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 130.750s 2320.016us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 186.940s 3103.866us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 124.270s 2902.795us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9886.800s 68651.725us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1143.110s 6788.783us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 415.330s 5979.790us 0 1 0.00
rom_e2e_jtag_debug_dev 649.390s 15191.384us 0 1 0.00
rom_e2e_jtag_debug_rma 213.190s 4567.946us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 77.040s 2361.767us 0 1 0.00
rom_e2e_jtag_inject_dev 64.890s 2882.152us 0 1 0.00
rom_e2e_jtag_inject_rma 86.920s 2664.932us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 123.586s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 274.960s 3666.187us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 320.340s 3353.017us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 727.250s 4481.462us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1262.210s 9365.099us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 218.180s 2508.546us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 617.120s 5703.982us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 77.990s 2297.786us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 211.240s 3379.419us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 344.250s 6069.155us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 269.170s 4111.372us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1114.140s 12929.384us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 415.330s 5979.790us 0 1 0.00
rom_e2e_jtag_debug_dev 649.390s 15191.384us 0 1 0.00
rom_e2e_jtag_debug_rma 213.190s 4567.946us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 329.980s 5293.874us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 386.890s 5800.248us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5566.090s 38366.576us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5566.090s 38366.576us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 192.900s 3381.375us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 359.990s 4407.505us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3233.320s 19152.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 188.560s 2996.669us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 21.740s 10.400us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 6.950s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 156.780s 2643.500us 1 1 100.00
chip_sw_otp_ctrl_descrambling 178.760s 3348.209us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 245.950s 3725.965us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 9.886s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 167.690s 2733.592us 1 1 100.00
ate_bootstrap_flash_erase 630.060s 10010.280us 0 1 0.00
ate_bootstrap_one_frame 6479.410s 43223.371us 1 1 100.00
ate_bootstrap_disjoint 9493.470s 78856.179us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 32603202248214802328143117088008593164916779260238123305343716249078195765253 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 60238552812915535897150251123477560278346903295220302516094762610447668281012 None
Another command (pid=373809) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=456600) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=454815) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 74357496503122536114623152414327956102482366248613310125571305470237778060012 None
Another command (pid=610914) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=594180) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=610354) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 14263933067667112775463781048245974585467988057008450712884974417273041355573 None
---- STDERR ----
Another command (pid=620252) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 38733563517046055888532460005709767856623639234159864609061607607526189641457 None
---- STDERR ----
Another command (pid=616513) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=628167) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 88090457956089408017023098750666239683251623362964093847227578631528372552046 None
---- STDERR ----
Another command (pid=630031) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=627029) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 3080185686686964167915715075625193204341154025469899125700654636136575971656 None
Another command (pid=373809) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=456600) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=454815) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 85048420629755808514437517006669240268353301377830926190262583909011377715107 None
Another command (pid=588787) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=610416) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=544607) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 412859812378848557763895350247080731317379631612179012535374117915797586956 None
Another command (pid=671633) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=674568) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=678144) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 115154093704761884536911180936141210829671482688649353270920315171729505751293 None
Another command (pid=610416) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=544607) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=620252) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 79222992525752139601953920311252888586428788650038029975849280863823778371574 None
Another command (pid=465133) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=592894) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=596748) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 3992306576683542344154651346859552963285614879522817266799075925864616603813 None
Another command (pid=619849) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=645340) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=646464) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 40012226219682941689685700937211888265780939902180374642560915018854889527647 None
Another command (pid=697242) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=757022) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=749569) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 97471950298842964787472120541635957240467808168734829704640606574297851640118 None
Another command (pid=615388) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=616513) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=565038) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 59752656495659563042286522436997333256975620534195303823972517943122260973489 None
---- STDERR ----
Another command (pid=465133) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 20786846936276487795369009574959320644725621159129132441018477910024745916 None
---- STDERR ----
Another command (pid=628167) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 71386594304342251314669730398586964312978056173941192653748579058417851063650 None
---- STDERR ----
Another command (pid=372765) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 67447515817310031641394970121234981580982851769446239746482298107605092857156 None
Another command (pid=642222) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=619849) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=645340) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 30621102378255195432418053869544242759881664296780726940308839020325353119638 None
Another command (pid=465680) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=466173) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=575744) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 56939414360490791301126445389679516863856418168974141534801625706724555969256 None
Another command (pid=463711) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=463112) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=466542) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 40470909109250307596687338079668998360753075422122659028063971258699671822837 None
Another command (pid=574114) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=413739) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=589841) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 60981641201202780529194562012157607060778480836520933304312420627167350031492 None
Another command (pid=463112) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=466542) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=465680) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 31723872003615508999572589482075157827515086209586601271952507231508170577325 None
---- STDERR ----
Another command (pid=372765) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 64183985474407492826617910275505534316405522014049233427301909109273523879531 None
Another command (pid=507929) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=464151) is running. Waiting for it to complete on the server (server_pid=310318)...
Another command (pid=576924) is running. Waiting for it to complete on the server (server_pid=310318)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 6 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 112455284420444841561933414907775046292179360017106855568211784776226269496885 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 101877648715900899372010600072524175502995995960475937956504215609924718237795 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 55652332198763953885647033661435130345214417579521129373259634940320409488599 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 71326573446150101062483660471819731274508333333520627777860961461863857435647 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 26653363395544904271826406932616570474809259480188877345532167742848652015827 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 39445633686976641312279843858268231990510925768798672136369722560580830016746 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 17546936872800761063643228435135450019866546261319986806188757057830036385878 373
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 44827162314814510605409085542589081541527030299214073866655476698985101975501 373
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 88630666930277489737102671887579515740641369802307697492760632156796278452156 372
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 73135669681480816984061650786699338405483138557937401933306822850816318521440 333
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 75911982343755840550499218091690332683580552340052046782290534656110372790786 328
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 89337411482962935423951881307258907165010586667852784669905122188914393202545 328
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 24127001080889171778244073121819618615058022204882286974530847936816823290949 369
UVM_INFO @ 7796.691513 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 35119975923950566920335501696460055251064608520202085858875940994623044659953 369
UVM_INFO @ 11815.870380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 106979514156657354391496192427373317829472401602461528040273490691825060328654 341
UVM_INFO @ 6679.244589 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 18020146667727536551544329001955748729790648521974473656268121011956753669695 327
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 19089877882399082720987867098747286474942820645720449504626749147928133406823 331
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 102917395512708245516533228059658096227790461760729079901099119698629721586768 330
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 2 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 16101222921917254718988935875543111049722625878949730022972773036374230347516 315
UVM_ERROR @ 5376.636000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5376.636000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 88457222212131986781697990592633913420174468773011729406086599919080635411667 330
UVM_ERROR @ 8313.340000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8313.340000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 95848956568088498691490565125792156034670317665277953626281363869066312165991 398
UVM_INFO @ 12026.731837 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 17359894831389763494350720700400737479270932956504566477527215444924805236426 339
UVM_INFO @ 20026.991176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 41507230838157138051149006386973166175128018147335717351212714744747737114597 217
TL item was: req: (cip_tl_seq_item@42716) { a_addr: 'h10350 a_data: 'h41b07961 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hb a_opcode: 'h4 a_user: 'h1868c d_param: 'h0 d_source: 'hb d_data: 'h13 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd7d a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2879.281720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 48070091631486606090056357766556103501831608196272334760396968087938492734408 224
TL item was: req: (cip_tl_seq_item@30900) { a_addr: 'h10634 a_data: 'h59500afa a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h25 a_opcode: 'h4 a_user: 'h1ae32 d_param: 'h0 d_source: 'h25 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2285.862652 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 82069662060169818402774326198855002821808925362598249158302667756716874193470 362
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 59797114376104897354936213364922528710932172843994976800017617420511281125187 325
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 11168075041382179405780923573218713349326023955730518647718601491865042169867 372
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 16688118365521217793030081435834163185416637474897396078658030756670148630631 333
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 60626197167159447907038420601934593915917669065386883913057209783223513300887 301
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] 1 test run
chip_sw_sleep_pin_mio_dio_val 48108718111710927777284057091804148108277672408793817553336656783811088325934 451
UVM_INFO @ 3142.001000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 105073848886226887325913633597174901635819668319159543496159909549734382718079 327
UVM_INFO @ 3348.850532 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 15167401381928548705871406557746274807039029667598642687158514743267730640121 309
UVM_INFO @ 2351.116244 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 86426132517140539861690245000885214570339420870853429193102794539693700270279 342
UVM_INFO @ 5472.562672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 58959560272576753883452579033284570143933446153132418093705786705949987993943 316
UVM_ERROR @ 3379.419194 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3379.419194 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 91175296658870805365049839093471635431059399239767126454806911641716576314243 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_walkthrough_testunlocks 71412385452785072613268412712629622791109447013653534111440092988004810415761 471
UVM_INFO @ 44832.895856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 50364866046358798063611904404600587613816022599436533598503867183212675523639 303
UVM_ERROR @ 1871.659020 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 1871.659020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 1 test run
chip_sw_pwrmgr_sleep_power_glitch_reset 17308442526512028741863648263754141139211056718999641382283609035584555731456 313
UVM_ERROR @ 3335.991800 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3335.991800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 23822546466785597152245920540155816751718565528649462702095878130570413879250 332
UVM_INFO @ 34500.416243 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:372)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 77953678355567835637948193849594783302615907779693018468893278592546844556161 307
UVM_INFO @ 3107.249528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 54605539997053641409670314577349648295634396343170527969338586663206500419489 308
UVM_INFO @ 3058.809912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 9242754469258240039996604662888858010555350848270892552910682952744310359564 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 31180913799106399671124760324667944797818679918543406888754261908449479759755 343
UVM_INFO @ 3666.187032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. 1 test run
chip_sw_rv_dm_access_after_wakeup 84990053758997662294272431976750848692832916397989999172974890646580471806081 329
UVM_INFO @ 13229.777419 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(outstanding_reqs_d <= MAX_REQS)' 1 test run
chip_sw_rv_core_ibex_lockstep_glitch 29453515527899167759443292403488794337112162539613916555801220308866041137709 322
UVM_ERROR @ 2902.795384 us: (tlul_adapter_host.sv:188) [ASSERT FAILED] DontExceeedMaxReqs
UVM_INFO @ 2902.795384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_idle_load 78842838442857360956333536335741826818911650302085979496801870522433235860036 318
UVM_INFO @ 15147.726192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_sleep_load 60844788632973329342735792835682187091296721349194049373775698672211452842371 329
UVM_INFO @ 14644.825088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 41003085472147072753748030548744744582222693077488753186163865808124288801426 327
UVM_INFO @ 9962.024607 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 18081890185436359256343023558597962735261149086950541899285163239316401747702 277
UVM_INFO @ 10010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 18511645661937636570877356651171796932541970311689450274762651064601222216035 325
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 28705353042159554755841313197691476539714481949945957135318079699120705006214 326
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! 1 test run
rom_e2e_jtag_debug_dev 37101158967408864304539578263940451340289979223315813458503005187821770327417 330
UVM_INFO @ 15191.383613 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 113686457567621969163693423809714470506667884097860015573370280002559278124095 327
UVM_ERROR @ 4472.889200 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4472.889200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---