Simulation Results: clkmgr

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.05 %
  • code
  • 96.68 %
  • assert
  • 93.79 %
  • func
  • 82.68 %
  • line
  • 96.83 %
  • branch
  • 96.91 %
  • cond
  • 90.79 %
  • toggle
  • 98.87 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.760s 51.464us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.750s 57.775us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.790s 27.717us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 2.680s 240.721us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.980s 19.265us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.510s 162.116us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.790s 27.717us 1 1 100.00
clkmgr_csr_aliasing 0.980s 19.265us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.710s 41.986us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.800s 30.546us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.710s 13.358us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.750s 23.279us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.760s 51.464us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 1.670s 336.298us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.590s 1710.707us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 1.670s 336.298us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 14.100s 3481.048us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.800s 17.185us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.600s 82.396us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.600s 82.396us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.750s 57.775us 1 1 100.00
clkmgr_csr_rw 0.790s 27.717us 1 1 100.00
clkmgr_csr_aliasing 0.980s 19.265us 1 1 100.00
clkmgr_same_csr_outstanding 1.000s 68.134us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.750s 57.775us 1 1 100.00
clkmgr_csr_rw 0.790s 27.717us 1 1 100.00
clkmgr_csr_aliasing 0.980s 19.265us 1 1 100.00
clkmgr_same_csr_outstanding 1.000s 68.134us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 23.880s 10455.585us 0 1 0.00
clkmgr_tl_intg_err 2.150s 258.569us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.490s 262.918us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.490s 262.918us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.490s 262.918us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.490s 262.918us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.670s 3.219us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.150s 258.569us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 1.670s 336.298us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.590s 1710.707us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.490s 262.918us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.770s 65.784us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.630s 13.384us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.680s 18.008us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.930s 96.125us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.800s 28.988us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.790s 27.717us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 23.880s 10455.585us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.790s 27.717us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.790s 27.717us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 23.880s 10455.585us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 4.780s 1149.972us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 13.530s 1256.977us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 34865980758778087714784042261800589000282605617708038692753368301537032775795 75
UVM_INFO @ 3218571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 46157112577372364697986354838683181318164817513851949939221809291750117171527 197
UVM_INFO @ 10455585108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---