Simulation Results: csrng

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.30 %
  • code
  • 92.34 %
  • assert
  • 94.10 %
  • func
  • 72.45 %
  • block
  • 97.05 %
  • line
  • 97.73 %
  • branch
  • 92.68 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 24.346us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 25.111us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 3.000s 62.065us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 11.000s 294.961us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 5.000s 310.947us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 58.313us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 3.000s 62.065us 1 1 100.00
csrng_csr_aliasing 5.000s 310.947us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 2.000s 43.884us 1 1 100.00
alerts 1 1 100.00
csrng_alert 3.000s 38.792us 1 1 100.00
err 1 1 100.00
csrng_err 1.000s 21.671us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 3.000s 71.819us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 3.000s 71.819us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 242.000s 6532.032us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 14.523us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 49.780us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 8.000s 421.917us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 8.000s 421.917us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 25.111us 1 1 100.00
csrng_csr_rw 3.000s 62.065us 1 1 100.00
csrng_csr_aliasing 5.000s 310.947us 1 1 100.00
csrng_same_csr_outstanding 2.000s 18.313us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 25.111us 1 1 100.00
csrng_csr_rw 3.000s 62.065us 1 1 100.00
csrng_csr_aliasing 5.000s 310.947us 1 1 100.00
csrng_same_csr_outstanding 2.000s 18.313us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 4.000s 286.740us 1 1 100.00
csrng_tl_intg_err 4.000s 351.080us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 2.000s 6.478us 0 1 0.00
csrng_csr_rw 3.000s 62.065us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 3.000s 38.792us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 242.000s 6532.032us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 2.000s 43.884us 1 1 100.00
csrng_err 1.000s 21.671us 1 1 100.00
csrng_sec_cm 4.000s 286.740us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 2.000s 43.884us 1 1 100.00
csrng_err 1.000s 21.671us 1 1 100.00
csrng_sec_cm 4.000s 286.740us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 2.000s 43.884us 1 1 100.00
csrng_err 1.000s 21.671us 1 1 100.00
csrng_sec_cm 4.000s 286.740us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 2.000s 43.884us 1 1 100.00
csrng_err 1.000s 21.671us 1 1 100.00
csrng_sec_cm 4.000s 286.740us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 2.000s 43.884us 1 1 100.00
csrng_err 1.000s 21.671us 1 1 100.00
csrng_sec_cm 4.000s 286.740us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 3.000s 38.792us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 2.000s 43.884us 1 1 100.00
csrng_err 1.000s 21.671us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 242.000s 6532.032us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 3.000s 38.792us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 351.080us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 2.000s 43.884us 1 1 100.00
csrng_err 1.000s 21.671us 1 1 100.00
csrng_sec_cm 4.000s 286.740us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 2.000s 43.884us 1 1 100.00
csrng_err 1.000s 21.671us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 2.000s 43.884us 1 1 100.00
csrng_err 1.000s 21.671us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 2.000s 43.884us 1 1 100.00
csrng_err 1.000s 21.671us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 2.000s 43.884us 1 1 100.00
csrng_err 1.000s 21.671us 1 1 100.00
csrng_sec_cm 4.000s 286.740us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 2.000s 43.884us 1 1 100.00
csrng_err 1.000s 21.671us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 4.000s 147.474us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 83019266175191488113388326639552786315802363412331358201200408367779024065349 110
UVM_INFO @ 71819281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 68717802834963896504535375036989344422161626992139779775622652696918897270075 99
UVM_INFO @ 6478434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all_with_rand_reset 62118352002814538044545254222184918347752261782449100414173620223867325225032 108
UVM_INFO @ 147474162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---