Simulation Results: edn/edn0

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.37 %
  • code
  • 78.24 %
  • assert
  • 96.10 %
  • func
  • 78.77 %
  • line
  • 96.85 %
  • branch
  • 89.26 %
  • cond
  • 83.63 %
  • toggle
  • 74.71 %
  • FSM
  • 46.77 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.080s 16.803us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.870s 15.191us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.790s 58.637us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.600s 618.334us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.120s 19.591us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.050s 27.288us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.790s 58.637us 1 1 100.00
edn_csr_aliasing 1.120s 19.591us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.090s 75.377us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.090s 75.377us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.090s 75.377us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.880s 28.221us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.260s 76.703us 1 1 100.00
errs 1 1 100.00
edn_err 1.020s 43.309us 1 1 100.00
disable 2 2 100.00
edn_disable 0.720s 51.603us 1 1 100.00
edn_disable_auto_req_mode 0.930s 145.736us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.240s 872.440us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.840s 13.026us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.890s 37.021us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.900s 632.913us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.900s 632.913us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.870s 15.191us 1 1 100.00
edn_csr_rw 0.790s 58.637us 1 1 100.00
edn_csr_aliasing 1.120s 19.591us 1 1 100.00
edn_same_csr_outstanding 1.190s 35.615us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.870s 15.191us 1 1 100.00
edn_csr_rw 0.790s 58.637us 1 1 100.00
edn_csr_aliasing 1.120s 19.591us 1 1 100.00
edn_same_csr_outstanding 1.190s 35.615us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.410s 1035.290us 1 1 100.00
edn_tl_intg_err 1.810s 69.896us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.150s 22.158us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.260s 76.703us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.410s 1035.290us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.410s 1035.290us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.410s 1035.290us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.410s 1035.290us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.260s 76.703us 1 1 100.00
edn_sec_cm 3.410s 1035.290us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.260s 76.703us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.810s 69.896us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 9.850s 527.947us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 113484441227340654637032859909320143921564397598687404263303502719267784253945 178
UVM_INFO @ 527946989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---