Simulation Results: entropy_src/rng_4bits

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 76.37 %
  • code
  • 89.02 %
  • assert
  • 84.73 %
  • func
  • 55.36 %
  • block
  • 94.47 %
  • line
  • 97.19 %
  • branch
  • 86.75 %
  • toggle
  • 76.31 %
  • FSM
  • 95.83 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 32.696us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 1.000s 42.990us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 71.516us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 4.000s 194.725us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 125.342us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 9.203us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 71.516us 1 1 100.00
entropy_src_csr_aliasing 3.000s 125.342us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 32.696us 1 1 100.00
entropy_src_rng 171.000s 13033.331us 1 1 100.00
entropy_src_fw_ov 55.000s 14049.359us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 55.000s 14049.359us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 171.000s 13033.331us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 355.000s 14018.684us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 171.000s 13033.331us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 171.000s 13033.331us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 171.000s 13033.331us 1 1 100.00
entropy_src_intr 2.000s 61.878us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 171.000s 13033.331us 1 1 100.00
entropy_src_functional_alerts 4.000s 220.087us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 195.000s 13233.509us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 62.151us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 3.000s 51.125us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 35.705us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 1.000s 81.587us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 126.761us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 126.761us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 42.990us 1 1 100.00
entropy_src_csr_rw 1.000s 71.516us 1 1 100.00
entropy_src_csr_aliasing 3.000s 125.342us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 43.964us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 42.990us 1 1 100.00
entropy_src_csr_rw 1.000s 71.516us 1 1 100.00
entropy_src_csr_aliasing 3.000s 125.342us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 43.964us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 274.175us 1 1 100.00
entropy_src_tl_intg_err 3.000s 404.632us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 171.000s 13033.331us 1 1 100.00
entropy_src_cfg_regwen 1.000s 17.213us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 171.000s 13033.331us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 171.000s 13033.331us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 171.000s 13033.331us 1 1 100.00
entropy_src_fw_ov 55.000s 14049.359us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 62.151us 1 1 100.00
entropy_src_sec_cm 2.000s 274.175us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 62.151us 1 1 100.00
entropy_src_sec_cm 2.000s 274.175us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 171.000s 13033.331us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 62.151us 1 1 100.00
entropy_src_sec_cm 2.000s 274.175us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 62.151us 1 1 100.00
entropy_src_sec_cm 2.000s 274.175us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 62.151us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 4.000s 220.087us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 404.632us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 55.000s 13077.129us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 4.000s 394.237us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_hi_threshold 1 test run
entropy_src_stress_all_with_rand_reset 113382497981781248957296595725480779923978358479425071453703124193272545922948 123
UVM_INFO @ 394237418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_lo_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 7488853757940317752056120791565250583285415610525745258181386617019301403950 113
UVM_INFO @ 9203146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---