Simulation Results: flash_ctrl

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.75 %
  • code
  • 94.32 %
  • assert
  • 97.02 %
  • func
  • 95.91 %
  • line
  • 95.95 %
  • branch
  • 97.16 %
  • cond
  • 93.68 %
  • toggle
  • 97.74 %
  • FSM
  • 87.07 %
Validation stages
V1
100.00%
V2
98.28%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 91.070s 53.949us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 14.200s 18.865us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 21.580s 310.846us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.300s 72.243us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 22.960s 1259.843us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 17.500s 909.669us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.710s 97.573us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.300s 72.243us 1 1 100.00
flash_ctrl_csr_aliasing 17.500s 909.669us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.880s 36.144us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.000s 57.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 12.850s 33.712us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 33.330s 390.174us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1292.490s 139404.391us 1 1 100.00
flash_ctrl_hw_rma_reset 550.890s 80162.777us 1 1 100.00
flash_ctrl_lcmgr_intg 7.260s 145.335us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1535.980s 287184.503us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 191.910s 7368.350us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 8.850s 52.598us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1885.320s 234452.795us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 50.010s 3105.975us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 18.730s 84.689us 1 1 100.00
flash_ctrl_rw_evict_all_en 20.710s 31.601us 1 1 100.00
flash_ctrl_re_evict 15.520s 184.446us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 156.650s 3842.296us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 156.650s 3842.296us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 488.290s 25165.616us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 14.370s 438.985us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 144.030s 134.741us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 332.100s 2778.721us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 375.820s 4245.595us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 1155.910s 4523.868us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.750s 23.346us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 131.850s 5647.297us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.600s 18.609us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 5.710s 17.813us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 330.160s 1314.090us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 48.700s 3681.088us 1 1 100.00
flash_ctrl_otp_reset 63.640s 69.016us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1292.490s 139404.391us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 130.840s 2064.801us 1 1 100.00
flash_ctrl_intr_wr 48.130s 3763.030us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 148.060s 12096.640us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 109.300s 23474.845us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 39.290s 2456.967us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 35.840s 1420.100us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 11.190s 114.430us 1 1 100.00
flash_ctrl_ro_derr 102.190s 840.402us 1 1 100.00
flash_ctrl_rw_derr 161.600s 2496.166us 1 1 100.00
flash_ctrl_derr_detect 102.280s 712.320us 1 1 100.00
flash_ctrl_integrity 325.330s 37775.593us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.260s 141.515us 1 1 100.00
flash_ctrl_ro_serr 110.540s 1073.605us 1 1 100.00
flash_ctrl_rw_serr 130.430s 3835.464us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 49.230s 12144.953us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 46.510s 6447.569us 1 1 100.00
scramble 4 5 80.00
flash_ctrl_wo 3603.779s 0.000us 0 1 0.00
flash_ctrl_write_word_sweep 6.990s 80.332us 1 1 100.00
flash_ctrl_read_word_sweep 7.290s 30.532us 1 1 100.00
flash_ctrl_ro 88.460s 4599.550us 1 1 100.00
flash_ctrl_rw 381.100s 9257.116us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 23.580s 862.614us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 580.400s 59861.253us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 110.370s 10031.736us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.880s 73.294us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.030s 19.611us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 10.160s 144.440us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 10.160s 144.440us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 21.580s 310.846us 1 1 100.00
flash_ctrl_csr_rw 8.300s 72.243us 1 1 100.00
flash_ctrl_csr_aliasing 17.500s 909.669us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.370s 104.260us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 21.580s 310.846us 1 1 100.00
flash_ctrl_csr_rw 8.300s 72.243us 1 1 100.00
flash_ctrl_csr_aliasing 17.500s 909.669us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.370s 104.260us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 26.880s 68.317us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 26.880s 68.317us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 26.880s 68.317us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 26.880s 68.317us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 54.690s 275.321us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1754.070s 3330.175us 1 1 100.00
flash_ctrl_tl_intg_err 162.460s 2476.441us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 162.460s 2476.441us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 162.460s 2476.441us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 16.400s 71.140us 1 1 100.00
flash_ctrl_wr_intg 9.150s 300.797us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 91.070s 53.949us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 63.640s 69.016us 1 1 100.00
flash_ctrl_disable 10.600s 18.609us 1 1 100.00
flash_ctrl_sec_info_access 61.090s 33347.359us 1 1 100.00
flash_ctrl_connect 5.710s 17.813us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.810s 48.201us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.300s 72.243us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 26.880s 68.317us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.300s 72.243us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 26.880s 68.317us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.300s 72.243us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 26.880s 68.317us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.600s 18.609us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 16.400s 71.140us 1 1 100.00
flash_ctrl_access_after_disable 6.110s 23.604us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 16.000s 28.859us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.600s 18.609us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 14.370s 438.985us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 381.100s 9257.116us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 130.430s 3835.464us 1 1 100.00
flash_ctrl_rw_derr 161.600s 2496.166us 1 1 100.00
flash_ctrl_integrity 325.330s 37775.593us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1292.490s 139404.391us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1754.070s 3330.175us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1754.070s 3330.175us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1754.070s 3330.175us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1754.070s 3330.175us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 10.280s 874.116us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.630s 22.228us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.980s 26.428us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1754.070s 3330.175us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1754.070s 3330.175us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1754.070s 3330.175us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 27.850s 106.524us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 364.950s 3161.412us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 1 test run
flash_ctrl_wo 64450854920167884567444806246099951417175063169534477375339424503028755316910 None