Simulation Results: hmac

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.12 %
  • code
  • 97.21 %
  • assert
  • 97.38 %
  • func
  • 42.78 %
  • line
  • 99.74 %
  • branch
  • 99.17 %
  • cond
  • 95.96 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 3.630s 125.587us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 225.480us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.790s 36.244us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.960s 911.046us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.520s 1442.969us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.240s 85.207us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.790s 36.244us 1 1 100.00
hmac_csr_aliasing 4.520s 1442.969us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 106.700s 157653.223us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 68.610s 12972.980us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 210.230s 170180.034us 1 1 100.00
hmac_test_sha384_vectors 481.620s 20275.905us 1 1 100.00
hmac_test_sha512_vectors 446.100s 79478.072us 1 1 100.00
hmac_test_hmac256_vectors 8.360s 1112.715us 1 1 100.00
hmac_test_hmac384_vectors 6.740s 252.214us 1 1 100.00
hmac_test_hmac512_vectors 7.850s 546.637us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 3.660s 206.022us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 828.890s 94288.571us 1 1 100.00
error 1 1 100.00
hmac_error 60.640s 2655.373us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 37.590s 8190.456us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 3.630s 125.587us 1 1 100.00
hmac_long_msg 106.700s 157653.223us 1 1 100.00
hmac_back_pressure 68.610s 12972.980us 1 1 100.00
hmac_datapath_stress 828.890s 94288.571us 1 1 100.00
hmac_burst_wr 3.660s 206.022us 1 1 100.00
hmac_stress_all 19.080s 3385.449us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 3.630s 125.587us 1 1 100.00
hmac_long_msg 106.700s 157653.223us 1 1 100.00
hmac_back_pressure 68.610s 12972.980us 1 1 100.00
hmac_datapath_stress 828.890s 94288.571us 1 1 100.00
hmac_wipe_secret 37.590s 8190.456us 1 1 100.00
hmac_test_sha256_vectors 210.230s 170180.034us 1 1 100.00
hmac_test_sha384_vectors 481.620s 20275.905us 1 1 100.00
hmac_test_sha512_vectors 446.100s 79478.072us 1 1 100.00
hmac_test_hmac256_vectors 8.360s 1112.715us 1 1 100.00
hmac_test_hmac384_vectors 6.740s 252.214us 1 1 100.00
hmac_test_hmac512_vectors 7.850s 546.637us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 3.630s 125.587us 1 1 100.00
hmac_long_msg 106.700s 157653.223us 1 1 100.00
hmac_back_pressure 68.610s 12972.980us 1 1 100.00
hmac_datapath_stress 828.890s 94288.571us 1 1 100.00
hmac_burst_wr 3.660s 206.022us 1 1 100.00
hmac_error 60.640s 2655.373us 1 1 100.00
hmac_wipe_secret 37.590s 8190.456us 1 1 100.00
hmac_test_sha256_vectors 210.230s 170180.034us 1 1 100.00
hmac_test_sha384_vectors 481.620s 20275.905us 1 1 100.00
hmac_test_sha512_vectors 446.100s 79478.072us 1 1 100.00
hmac_test_hmac256_vectors 8.360s 1112.715us 1 1 100.00
hmac_test_hmac384_vectors 6.740s 252.214us 1 1 100.00
hmac_test_hmac512_vectors 7.850s 546.637us 1 1 100.00
hmac_stress_all 19.080s 3385.449us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 19.080s 3385.449us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.860s 265.067us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.630s 19.679us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.440s 3135.481us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.440s 3135.481us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 225.480us 1 1 100.00
hmac_csr_rw 0.790s 36.244us 1 1 100.00
hmac_csr_aliasing 4.520s 1442.969us 1 1 100.00
hmac_same_csr_outstanding 1.680s 199.202us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 225.480us 1 1 100.00
hmac_csr_rw 0.790s 36.244us 1 1 100.00
hmac_csr_aliasing 4.520s 1442.969us 1 1 100.00
hmac_same_csr_outstanding 1.680s 199.202us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.140s 914.964us 1 1 100.00
hmac_tl_intg_err 2.110s 1023.782us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.110s 1023.782us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 3.630s 125.587us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 6.630s 598.996us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 73.340s 9664.352us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.070s 51.831us 1 1 100.00