Simulation Results

Simulation Results: i2c

01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
84.56 %

code
78.32 %

assert
95.98 %

func
79.39 %

line
96.45 %

branch
92.41 %

cond
85.16 %

toggle
72.95 %

FSM
44.64 %

Validation stages

V1		100.00%
V2		92.68%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	46.260s	7272.314us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	20.240s	2198.840us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.820s	21.479us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.760s	27.134us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.050s	336.963us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.370s	88.511us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.910s	19.104us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.760s	27.134us	1	1	100.00
	i2c_csr_aliasing	1.370s	88.511us	1	1	100.00

38/41 passed

92.68 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.910s	17.855us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	96.220s	13644.262us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	215.500s	18224.437us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.960s	97.468us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	52.640s	7546.423us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	55.840s	13225.768us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.170s	147.586us	1	1	100.00
	i2c_host_fifo_fmt_empty	5.890s	4499.390us	1	1	100.00
	i2c_host_fifo_reset_rx	6.540s	210.055us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	118.250s	3488.176us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	15.770s	507.785us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	2.140s	185.225us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.860s	1895.957us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	15.900s	3873.461us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.990s	5075.743us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	43.250s	15665.336us	1	1	100.00
	i2c_target_intr_smoke	5.180s	25506.635us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.160s	452.013us	1	1	100.00
	i2c_target_fifo_reset_tx	1.020s	125.573us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	207.280s	35371.487us	1	1	100.00
	i2c_target_stress_rd	43.250s	15665.336us	1	1	100.00
	i2c_target_intr_stress_wr	300.450s	22502.076us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	6.000s	6150.294us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	23.630s	3164.171us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.450s	3239.652us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.910s	1488.430us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.190s	3643.036us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.190s	377.111us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	215.500s	18224.437us	1	1	100.00
	i2c_host_perf_precise	6.750s	589.271us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	15.770s	507.785us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	6.130s	595.079us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.850s	488.160us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.460s	1759.122us	1	1	100.00
	i2c_target_nack_txstretch	1.480s	255.797us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	4.310s	1139.796us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	2.350s	469.089us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.830s	45.777us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.850s	15.553us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.270s	40.866us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.270s	40.866us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.820s	21.479us	1	1	100.00
	i2c_csr_rw	0.760s	27.134us	1	1	100.00
	i2c_csr_aliasing	1.370s	88.511us	1	1	100.00
	i2c_same_csr_outstanding	1.020s	35.328us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.820s	21.479us	1	1	100.00
	i2c_csr_rw	0.760s	27.134us	1	1	100.00
	i2c_csr_aliasing	1.370s	88.511us	1	1	100.00
	i2c_same_csr_outstanding	1.020s	35.328us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.420s	111.532us	1	1	100.00
	i2c_sec_cm	1.160s	308.674us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.420s	111.532us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	31.760s	3564.230us	1
target_error_intr				1
	i2c_target_unexp_stop	1.170s	317.859us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	1.080s	28.191us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	101455874337306987389039985180408509169048262736229415511690221415794519280059	96	UVM_INFO @ 17854579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	30993439736770857196198112632973504184453106004329501303899522168453956638495	85	UVM_INFO @ 28191396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.fmtfull (addr=, Comparison=CompareOpEq, exp_data=, call_count=724)				1 test run
	i2c_host_stress_all	55836540390917635872507783262007653740177133845538136431058325118806041815235	199	UVM_INFO @ 13644262158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	79308762865899613554089549161263621676777737568938544669962445372364856401481	84	UVM_INFO @ 1895956522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	102432885704104158904309707505942788053826208959738034342702275186859007795800	78	UVM_INFO @ 317858657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	89543077447734106199754807692981504450400778254552071321053654078271032573312	96	UVM_INFO @ 3564230167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---