Simulation Results: keymgr

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.48 %
  • code
  • 92.72 %
  • assert
  • 97.49 %
  • func
  • 57.24 %
  • line
  • 98.68 %
  • branch
  • 97.44 %
  • cond
  • 93.24 %
  • toggle
  • 90.53 %
  • FSM
  • 83.72 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.160s 55.690us 1 1 100.00
random 1 1 100.00
keymgr_random 4.830s 209.602us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.350s 29.686us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.140s 32.492us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 14.850s 8075.044us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 7.600s 427.103us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.490s 59.673us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.140s 32.492us 1 1 100.00
keymgr_csr_aliasing 7.600s 427.103us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 3.850s 90.990us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 2.080s 30.547us 1 1 100.00
keymgr_sideload_kmac 3.030s 449.609us 1 1 100.00
keymgr_sideload_aes 3.620s 235.354us 1 1 100.00
keymgr_sideload_otbn 2.630s 269.106us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 2.970s 257.995us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 3.030s 115.035us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.750s 84.008us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 7.380s 280.414us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 1.810s 118.245us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.560s 171.473us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 15.580s 2052.430us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 1.090s 100.138us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.980s 46.959us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.400s 336.851us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.400s 336.851us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.350s 29.686us 1 1 100.00
keymgr_csr_rw 1.140s 32.492us 1 1 100.00
keymgr_csr_aliasing 7.600s 427.103us 1 1 100.00
keymgr_same_csr_outstanding 2.830s 137.658us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.350s 29.686us 1 1 100.00
keymgr_csr_rw 1.140s 32.492us 1 1 100.00
keymgr_csr_aliasing 7.600s 427.103us 1 1 100.00
keymgr_same_csr_outstanding 2.830s 137.658us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 12.710s 2336.943us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 12.710s 2336.943us 1 1 100.00
keymgr_tl_intg_err 2.900s 546.642us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.250s 187.930us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.250s 187.930us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.250s 187.930us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.250s 187.930us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 4.450s 425.571us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 12.710s 2336.943us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 12.710s 2336.943us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 2.900s 546.642us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.250s 187.930us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 3.850s 90.990us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 4.830s 209.602us 1 1 100.00
keymgr_csr_rw 1.140s 32.492us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 4.830s 209.602us 1 1 100.00
keymgr_csr_rw 1.140s 32.492us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 4.830s 209.602us 1 1 100.00
keymgr_csr_rw 1.140s 32.492us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 3.030s 115.035us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.810s 118.245us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.810s 118.245us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 4.830s 209.602us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 3.730s 212.288us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 12.710s 2336.943us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 12.710s 2336.943us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 12.710s 2336.943us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 3.600s 218.340us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 3.030s 115.035us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 12.710s 2336.943us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 12.710s 2336.943us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 12.710s 2336.943us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.600s 218.340us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.600s 218.340us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 12.710s 2336.943us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.600s 218.340us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 12.710s 2336.943us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 3.600s 218.340us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 4.720s 194.643us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 51095339027590049329787264644990827673670858011156523479789631072742581570234 450
UVM_INFO @ 194643086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---