Simulation Results

Simulation Results: kmac/unmasked

01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
80.99 %

code
67.62 %

assert
97.37 %

func
77.99 %

line
94.10 %

branch
88.66 %

cond
86.33 %

toggle
27.41 %

FSM
41.61 %

Validation stages

V1		100.00%
V2		75.86%
V2S		87.50%
V3		0.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	kmac_smoke	9.560s	314.214us	1	1	100.00
csr_hw_reset				1	1	100.00
	kmac_csr_hw_reset	0.800s	27.523us	1	1	100.00
csr_rw				1	1	100.00
	kmac_csr_rw	1.090s	31.254us	1	1	100.00
csr_bit_bash				1	1	100.00
	kmac_csr_bit_bash	9.610s	914.460us	1	1	100.00
csr_aliasing				1	1	100.00
	kmac_csr_aliasing	5.330s	317.772us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	kmac_csr_mem_rw_with_rand_reset	1.350s	50.108us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	kmac_csr_rw	1.090s	31.254us	1	1	100.00
	kmac_csr_aliasing	5.330s	317.772us	1	1	100.00
mem_walk				1	1	100.00
	kmac_mem_walk	0.710s	38.410us	1	1	100.00
mem_partial_access				1	1	100.00
	kmac_mem_partial_access	1.390s	71.291us	1	1	100.00

22/29 passed

75.86 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
long_msg_and_output				1	1	100.00
	kmac_long_msg_and_output	1376.090s	95890.722us	1	1	100.00
burst_write				1	1	100.00
	kmac_burst_write	745.330s	268376.199us	1	1	100.00
test_vectors				8	8	100.00
	kmac_test_vectors_sha3_224	1362.880s	29073.593us	1	1	100.00
	kmac_test_vectors_sha3_256	29.540s	5789.072us	1	1	100.00
	kmac_test_vectors_sha3_384	22.830s	1844.606us	1	1	100.00
	kmac_test_vectors_sha3_512	14.480s	2024.988us	1	1	100.00
	kmac_test_vectors_shake_128	144.050s	13626.434us	1	1	100.00
	kmac_test_vectors_shake_256	1232.690s	100808.517us	1	1	100.00
	kmac_test_vectors_kmac	1.870s	596.926us	1	1	100.00
	kmac_test_vectors_kmac_xof	3.100s	278.178us	1	1	100.00
sideload				1	1	100.00
	kmac_sideload	188.330s	14865.776us	1	1	100.00
app				0	1	0.00
	kmac_app	3.980s	258.853us	0	1	0.00
app_with_partial_data				0	1	0.00
	kmac_app_with_partial_data	2.920s	2629.143us	0	1	0.00
entropy_refresh				0	1	0.00
	kmac_entropy_refresh	1.530s	388.579us	0	1	0.00
error				1	1	100.00
	kmac_error	43.620s	8385.796us	1	1	100.00
key_error				0	1	0.00
	kmac_key_error	0.980s	37.415us	0	1	0.00
sideload_invalid				0	1	0.00
	kmac_sideload_invalid	1.020s	11.831us	0	1	0.00
edn_timeout_error				1	1	100.00
	kmac_edn_timeout_error	30.860s	9151.712us	1	1	100.00
entropy_mode_error				1	1	100.00
	kmac_entropy_mode_error	26.780s	2657.749us	1	1	100.00
entropy_ready_error				0	1	0.00
	kmac_entropy_ready_error	0.970s	21.741us	0	1	0.00
lc_escalation				1	1	100.00
	kmac_lc_escalation	1.120s	82.767us	1	1	100.00
stress_all				0	1	0.00
	kmac_stress_all	26.760s	4160.487us	0	1	0.00
intr_test				1	1	100.00
	kmac_intr_test	0.890s	31.689us	1	1	100.00
alert_test				1	1	100.00
	kmac_alert_test	0.950s	15.158us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	kmac_tl_errors	3.710s	970.506us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	kmac_tl_errors	3.710s	970.506us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	kmac_csr_hw_reset	0.800s	27.523us	1	1	100.00
	kmac_csr_rw	1.090s	31.254us	1	1	100.00
	kmac_csr_aliasing	5.330s	317.772us	1	1	100.00
	kmac_same_csr_outstanding	1.320s	211.541us	1	1	100.00
tl_d_partial_access				4	4	100.00
	kmac_csr_hw_reset	0.800s	27.523us	1	1	100.00
	kmac_csr_rw	1.090s	31.254us	1	1	100.00
	kmac_csr_aliasing	5.330s	317.772us	1	1	100.00
	kmac_same_csr_outstanding	1.320s	211.541us	1	1	100.00

V2S

7/8 passed

87.50 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				1	1	100.00
	kmac_shadow_reg_errors	1.620s	110.222us	1	1	100.00
shadow_reg_read_clear_staged_value				1	1	100.00
	kmac_shadow_reg_errors	1.620s	110.222us	1	1	100.00
shadow_reg_storage_error				1	1	100.00
	kmac_shadow_reg_errors	1.620s	110.222us	1	1	100.00
shadowed_reset_glitch				1	1	100.00
	kmac_shadow_reg_errors	1.620s	110.222us	1	1	100.00
shadow_reg_update_error_with_csr_rw				1	1	100.00
	kmac_shadow_reg_errors_with_csr_rw	2.470s	377.598us	1	1	100.00
tl_intg_err				2	2	100.00
	kmac_sec_cm	29.790s	9384.513us	1	1	100.00
	kmac_tl_intg_err	4.500s	911.455us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	kmac_tl_intg_err	4.500s	911.455us	1	1	100.00
sec_cm_lc_escalate_en_intersig_mubi				1	1	100.00
	kmac_lc_escalation	1.120s	82.767us	1	1	100.00
sec_cm_sw_key_key_masking				1	1	100.00
	kmac_smoke	9.560s	314.214us	1	1	100.00
sec_cm_key_sideload				1	1	100.00
	kmac_sideload	188.330s	14865.776us	1	1	100.00
sec_cm_cfg_shadowed_config_shadow				1	1	100.00
	kmac_shadow_reg_errors	1.620s	110.222us	1	1	100.00
sec_cm_fsm_sparse				1	1	100.00
	kmac_sec_cm	29.790s	9384.513us	1	1	100.00
sec_cm_ctr_redun				1	1	100.00
	kmac_sec_cm	29.790s	9384.513us	1	1	100.00
sec_cm_packer_ctr_redun				1	1	100.00
	kmac_sec_cm	29.790s	9384.513us	1	1	100.00
sec_cm_cfg_shadowed_config_regwen				1	1	100.00
	kmac_smoke	9.560s	314.214us	1	1	100.00
sec_cm_fsm_global_esc				1	1	100.00
	kmac_lc_escalation	1.120s	82.767us	1	1	100.00
sec_cm_fsm_local_esc				1	1	100.00
	kmac_sec_cm	29.790s	9384.513us	1	1	100.00
sec_cm_absorbed_ctrl_mubi				0	1	0.00
	kmac_mubi	7.100s	1079.253us	0	1	0.00
sec_cm_sw_cmd_ctrl_sparse				1	1	100.00
	kmac_smoke	9.560s	314.214us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	kmac_stress_all_with_rand_reset	19.620s	2258.944us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [] vs []) Mismatch between unmasked_digest[] and dpi_digest[*]				6 test runs
	kmac_sideload_invalid	24273198248016990085202771493246890203634032523700486256169900656874742455519	76	UVM_INFO @ 11831250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_app	37022069953185764491355934662125532359795422129013757654170586503504571783717	79	UVM_INFO @ 258853453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_app_with_partial_data	43787089484011195946184072442402990496336893754281778778692847585640179796172	77	UVM_INFO @ 2629143368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_entropy_refresh	42271275999716518856674740059393885009111880659526478940365753044921305816300	77	UVM_INFO @ 388578932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_entropy_ready_error	86491727858627778011545903626155199997346917547889816374858741543991954015904	77	UVM_INFO @ 21741183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_stress_all	84144330186320762145797708734255732907406592134507925384686189610288613924513	98	UVM_INFO @ 4160486806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err)				1 test run
	kmac_mubi	587624635430591676347332529112904210677785067601335857313428502464933019235	81	UVM_INFO @ 1079252990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))'				1 test run
	kmac_key_error	72838739416587488855561475759767907664375384414373138490265167675017670170166	78	UVM_ERROR @ 37414527 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A UVM_INFO @ 37414527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	kmac_stress_all_with_rand_reset	12337870647648570578814194778960762630695457886996617559773852177971238511062	119	UVM_INFO @ 2258944111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---