Simulation Results: lc_ctrl/volatile_unlock_disabled

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.28 %
  • code
  • 83.88 %
  • assert
  • 94.27 %
  • func
  • 92.70 %
  • line
  • 97.15 %
  • branch
  • 93.56 %
  • cond
  • 79.79 %
  • toggle
  • 87.24 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.200s 161.552us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.860s 104.326us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.100s 14.695us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.250s 114.494us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.560s 28.412us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.170s 35.345us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.100s 14.695us 1 1 100.00
lc_ctrl_csr_aliasing 1.560s 28.412us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.270s 192.009us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.060s 497.946us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.060s 77.753us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.300s 86.320us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.360s 260.095us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 9.140s 830.530us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.360s 260.095us 1 1 100.00
lc_ctrl_prog_failure 1.300s 86.320us 1 1 100.00
lc_ctrl_errors 9.140s 830.530us 1 1 100.00
lc_ctrl_security_escalation 4.230s 809.270us 1 1 100.00
lc_ctrl_jtag_state_failure 23.860s 11375.907us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.080s 131.789us 1 1 100.00
lc_ctrl_jtag_errors 34.320s 6532.835us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 12.460s 1272.982us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.620s 1814.634us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.080s 131.789us 1 1 100.00
lc_ctrl_jtag_errors 34.320s 6532.835us 1 1 100.00
lc_ctrl_jtag_access 7.200s 1757.104us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.450s 1286.423us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.770s 79.264us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.640s 88.327us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.590s 673.046us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.420s 184.977us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.050s 113.982us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.610s 372.517us 1 1 100.00
lc_ctrl_jtag_alert_test 1.300s 168.563us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 12.850s 7058.483us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.970s 19.524us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 28.630s 3269.925us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.170s 63.239us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.800s 141.332us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.800s 141.332us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.860s 104.326us 1 1 100.00
lc_ctrl_csr_rw 1.100s 14.695us 1 1 100.00
lc_ctrl_csr_aliasing 1.560s 28.412us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.440s 48.372us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.860s 104.326us 1 1 100.00
lc_ctrl_csr_rw 1.100s 14.695us 1 1 100.00
lc_ctrl_csr_aliasing 1.560s 28.412us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.440s 48.372us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.470s 233.935us 1 1 100.00
lc_ctrl_tl_intg_err 1.560s 374.166us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.560s 374.166us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.060s 497.946us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.360s 260.095us 1 1 100.00
lc_ctrl_sec_cm 5.470s 233.935us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.360s 260.095us 1 1 100.00
lc_ctrl_sec_cm 5.470s 233.935us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.360s 260.095us 1 1 100.00
lc_ctrl_sec_cm 5.470s 233.935us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.360s 260.095us 1 1 100.00
lc_ctrl_sec_cm 5.470s 233.935us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.360s 260.095us 1 1 100.00
lc_ctrl_sec_cm 5.470s 233.935us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.360s 260.095us 1 1 100.00
lc_ctrl_sec_cm 5.470s 233.935us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.360s 260.095us 1 1 100.00
lc_ctrl_sec_cm 5.470s 233.935us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.360s 260.095us 1 1 100.00
lc_ctrl_sec_cm 5.470s 233.935us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.230s 809.270us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.270s 192.009us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.620s 1814.634us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.330s 206.759us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.330s 206.759us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.950s 1098.191us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.610s 940.542us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.610s 940.542us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 70.460s 5753.723us 1 1 100.00