Simulation Results: lc_ctrl/volatile_unlock_enabled

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.05 %
  • code
  • 84.23 %
  • assert
  • 94.97 %
  • func
  • 93.95 %
  • line
  • 97.13 %
  • branch
  • 93.37 %
  • cond
  • 79.34 %
  • toggle
  • 86.83 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.550s 22.529us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.020s 29.586us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.040s 35.781us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.840s 934.610us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.450s 355.098us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.600s 87.852us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.040s 35.781us 1 1 100.00
lc_ctrl_csr_aliasing 1.450s 355.098us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.140s 194.241us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.770s 2848.438us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.900s 14.391us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.020s 669.389us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.800s 227.617us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.230s 364.368us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.800s 227.617us 1 1 100.00
lc_ctrl_prog_failure 2.020s 669.389us 1 1 100.00
lc_ctrl_errors 5.230s 364.368us 1 1 100.00
lc_ctrl_security_escalation 7.550s 501.483us 1 1 100.00
lc_ctrl_jtag_state_failure 22.920s 2916.998us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.640s 328.112us 1 1 100.00
lc_ctrl_jtag_errors 31.820s 6397.413us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 7.730s 4124.597us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.130s 865.380us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.640s 328.112us 1 1 100.00
lc_ctrl_jtag_errors 31.820s 6397.413us 1 1 100.00
lc_ctrl_jtag_access 3.070s 323.215us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 18.330s 926.277us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.440s 59.178us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.050s 143.976us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.550s 1198.742us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.210s 1433.545us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.480s 22.931us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.670s 1014.587us 1 1 100.00
lc_ctrl_jtag_alert_test 0.900s 31.652us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.580s 404.494us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.030s 24.279us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 37.770s 12541.889us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.840s 14.669us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.630s 65.788us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.630s 65.788us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.020s 29.586us 1 1 100.00
lc_ctrl_csr_rw 1.040s 35.781us 1 1 100.00
lc_ctrl_csr_aliasing 1.450s 355.098us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.580s 168.735us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.020s 29.586us 1 1 100.00
lc_ctrl_csr_rw 1.040s 35.781us 1 1 100.00
lc_ctrl_csr_aliasing 1.450s 355.098us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.580s 168.735us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.560s 124.698us 1 1 100.00
lc_ctrl_tl_intg_err 1.410s 62.668us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.410s 62.668us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.770s 2848.438us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.800s 227.617us 1 1 100.00
lc_ctrl_sec_cm 6.560s 124.698us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.800s 227.617us 1 1 100.00
lc_ctrl_sec_cm 6.560s 124.698us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.800s 227.617us 1 1 100.00
lc_ctrl_sec_cm 6.560s 124.698us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.800s 227.617us 1 1 100.00
lc_ctrl_sec_cm 6.560s 124.698us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.800s 227.617us 1 1 100.00
lc_ctrl_sec_cm 6.560s 124.698us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.800s 227.617us 1 1 100.00
lc_ctrl_sec_cm 6.560s 124.698us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.800s 227.617us 1 1 100.00
lc_ctrl_sec_cm 6.560s 124.698us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.800s 227.617us 1 1 100.00
lc_ctrl_sec_cm 6.560s 124.698us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.550s 501.483us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.140s 194.241us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.130s 865.380us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.260s 268.758us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.260s 268.758us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.170s 604.151us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.470s 276.133us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.470s 276.133us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 44.250s 1989.979us 1 1 100.00