Simulation Results: otp_ctrl

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.89 %
  • code
  • 78.49 %
  • assert
  • 94.50 %
  • func
  • 75.67 %
  • line
  • 88.64 %
  • branch
  • 83.26 %
  • cond
  • 90.05 %
  • toggle
  • 87.10 %
  • FSM
  • 43.40 %
Validation stages
V1
100.00%
V2
95.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.490s 56.999us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 5.580s 2478.091us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.440s 372.407us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.290s 82.719us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.290s 101.299us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.010s 370.484us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.110s 1744.858us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.290s 82.719us 1 1 100.00
otp_ctrl_csr_aliasing 5.010s 370.484us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.180s 39.338us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.210s 40.590us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 15.800s 3391.540us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.410s 184.921us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 8.120s 637.329us 1 1 100.00
otp_ctrl_check_fail 4.130s 255.665us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 7.150s 472.458us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 13.690s 7578.889us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 2.540s 93.273us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 12.380s 2284.505us 1 1 100.00
otp_ctrl_parallel_lc_esc 7.410s 1675.424us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 10.180s 2284.829us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 3.270s 126.122us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 34.240s 6363.564us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 142.620s 28109.639us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.320s 588.803us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.330s 160.887us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.890s 504.808us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.890s 504.808us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.440s 372.407us 1 1 100.00
otp_ctrl_csr_rw 1.290s 82.719us 1 1 100.00
otp_ctrl_csr_aliasing 5.010s 370.484us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.990s 405.051us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.440s 372.407us 1 1 100.00
otp_ctrl_csr_rw 1.290s 82.719us 1 1 100.00
otp_ctrl_csr_aliasing 5.010s 370.484us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.990s 405.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
otp_ctrl_tl_intg_err 6.760s 1048.297us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 6.760s 1048.297us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 5.580s 2478.091us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 5.580s 2478.091us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.410s 1675.424us 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.410s 1675.424us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.410s 1675.424us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.410s 1675.424us 1 1 100.00
otp_ctrl_macro_errs 3.270s 126.122us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.410s 1675.424us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.410s 1675.424us 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.410s 1675.424us 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.410s 1675.424us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.410s 1675.424us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.410s 1675.424us 1 1 100.00
otp_ctrl_macro_errs 3.270s 126.122us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.410s 1675.424us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.410s 1675.424us 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.410s 184.921us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 4.130s 255.665us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 13.690s 7578.889us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 13.690s 7578.889us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 13.690s 7578.889us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 13.690s 7578.889us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 13.690s 7578.889us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 5.580s 2478.091us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 13.690s 7578.889us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 5.580s 2478.091us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 98.980s 9992.864us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 7.150s 472.458us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 5.580s 2478.091us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 5.580s 2478.091us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 3.270s 126.122us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 10.760s 3657.769us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 52.080s 15763.051us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 86487803311395009687529950201353487309711741342662929035840197251560734869758 4260
UVM_INFO @ 255665334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all_with_rand_reset 83910873304023758753645292843001371143726378631054390636074467342225956786652 5766
UVM_INFO @ 15763050617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---