Simulation Results: pwrmgr

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.61 %
  • code
  • 95.79 %
  • assert
  • 98.69 %
  • func
  • 98.35 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.32 %
  • toggle
  • 91.15 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.640s 23.623us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.730s 115.839us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.730s 23.228us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.730s 183.809us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.940s 42.247us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.130s 49.422us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.730s 23.228us 1 1 100.00
pwrmgr_csr_aliasing 0.940s 42.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.690s 281.873us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.690s 281.873us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.800s 394.700us 1 1 100.00
pwrmgr_lowpower_invalid 0.670s 44.133us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 1.210s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.930s 456.683us 1 1 100.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 1.210s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.960s 175.301us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.640s 40.644us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.660s 38.146us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.080s 269.738us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.620s 34.428us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.340s 128.525us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.340s 128.525us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.730s 115.839us 1 1 100.00
pwrmgr_csr_rw 0.730s 23.228us 1 1 100.00
pwrmgr_csr_aliasing 0.940s 42.247us 1 1 100.00
pwrmgr_same_csr_outstanding 0.790s 79.333us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.730s 115.839us 1 1 100.00
pwrmgr_csr_rw 0.730s 23.228us 1 1 100.00
pwrmgr_csr_aliasing 0.940s 42.247us 1 1 100.00
pwrmgr_same_csr_outstanding 0.790s 79.333us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.000s 141.614us 1 1 100.00
pwrmgr_sec_cm 1.280s 304.920us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.280s 304.920us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.280s 304.920us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.000s 141.614us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.120s 772.070us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.960s 175.301us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.820s 1022.694us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.770s 118.237us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.700s 29.907us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.280s 304.920us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.280s 304.920us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.280s 304.920us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.680s 108.284us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.640s 66.981us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.020s 285.433us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.730s 23.228us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.730s 23.228us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.690s 1738.789us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 3.460s 2422.476us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_reset 36986543154167789847282183545089945793548264075161990191077466032759243580020 84
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---