Simulation Results: rom_ctrl/64kb

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.54 %
  • code
  • 95.48 %
  • assert
  • 97.24 %
  • func
  • 96.90 %
  • line
  • 99.33 %
  • branch
  • 99.27 %
  • cond
  • 97.47 %
  • toggle
  • 94.64 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 9.750s 1122.249us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.290s 539.440us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.190s 1026.044us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.400s 207.362us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.950s 453.153us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 9.940s 4200.303us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.190s 1026.044us 1 1 100.00
rom_ctrl_csr_aliasing 5.950s 453.153us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.680s 1023.945us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.180s 672.888us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 6.710s 172.811us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 26.370s 3146.697us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.800s 723.875us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.520s 1272.566us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.370s 3337.335us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.370s 3337.335us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.290s 539.440us 1 1 100.00
rom_ctrl_csr_rw 7.190s 1026.044us 1 1 100.00
rom_ctrl_csr_aliasing 5.950s 453.153us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.560s 209.666us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.290s 539.440us 1 1 100.00
rom_ctrl_csr_rw 7.190s 1026.044us 1 1 100.00
rom_ctrl_csr_aliasing 5.950s 453.153us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.560s 209.666us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.560s 2081.905us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 35.230s 12796.792us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 237.340s 1397.114us 1 1 100.00
rom_ctrl_tl_intg_err 53.990s 1707.947us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 237.340s 1397.114us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 237.340s 1397.114us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.560s 2081.905us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.560s 2081.905us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.560s 2081.905us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.560s 2081.905us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.560s 2081.905us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 237.340s 1397.114us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 237.340s 1397.114us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 9.750s 1122.249us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 9.750s 1122.249us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 9.750s 1122.249us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 53.990s 1707.947us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.560s 2081.905us 1 1 100.00
rom_ctrl_kmac_err_chk 12.800s 723.875us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.560s 2081.905us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.560s 2081.905us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.560s 2081.905us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 35.230s 12796.792us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 237.340s 1397.114us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 74.050s 10718.497us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 103355092526539394314706748597322765638434691966283640266363944238073521156025 79
UVM_INFO @ 172810979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---