Simulation Results: rstmgr

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.51 %
  • code
  • 99.32 %
  • assert
  • 98.93 %
  • func
  • 91.29 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.54 %
  • toggle
  • 99.41 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.370s 293.913us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.890s 127.152us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.890s 74.081us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.940s 1275.580us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.560s 151.397us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.000s 111.952us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.890s 74.081us 1 1 100.00
rstmgr_csr_aliasing 1.560s 151.397us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.790s 156.115us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.070s 566.027us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.850s 100.695us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.700s 2209.334us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.700s 2209.334us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.700s 2209.334us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.700s 2209.334us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 1.000s 215.409us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.800s 67.691us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.620s 280.912us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.620s 280.912us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.890s 127.152us 1 1 100.00
rstmgr_csr_rw 0.890s 74.081us 1 1 100.00
rstmgr_csr_aliasing 1.560s 151.397us 1 1 100.00
rstmgr_same_csr_outstanding 1.270s 233.458us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.890s 127.152us 1 1 100.00
rstmgr_csr_rw 0.890s 74.081us 1 1 100.00
rstmgr_csr_aliasing 1.560s 151.397us 1 1 100.00
rstmgr_same_csr_outstanding 1.270s 233.458us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 11.100s 8462.097us 1 1 100.00
rstmgr_tl_intg_err 2.430s 992.746us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 11.100s 8462.097us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 11.100s 8462.097us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.430s 992.746us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.430s 194.360us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 7.460s 2562.503us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.100s 301.458us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 11.100s 8462.097us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.890s 74.081us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.890s 74.081us 1 1 100.00