Simulation Results: rv_timer

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.92 %
  • code
  • 94.66 %
  • assert
  • 98.09 %
  • func
  • 95.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.030s 171.108us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.600s 70.004us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.600s 17.122us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.330s 194.031us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.780s 40.875us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.750s 31.505us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.600s 17.122us 1 1 100.00
rv_timer_csr_aliasing 0.780s 40.875us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.260s 167.147us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.210s 1521.673us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 112.860s 367875.405us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 112.860s 367875.405us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.310s 19658.480us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.620s 35.955us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.630s 18.157us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 0.970s 202.006us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 0.970s 202.006us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.600s 70.004us 1 1 100.00
rv_timer_csr_rw 0.600s 17.122us 1 1 100.00
rv_timer_csr_aliasing 0.780s 40.875us 1 1 100.00
rv_timer_same_csr_outstanding 0.670s 75.425us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.600s 70.004us 1 1 100.00
rv_timer_csr_rw 0.600s 17.122us 1 1 100.00
rv_timer_csr_aliasing 0.780s 40.875us 1 1 100.00
rv_timer_same_csr_outstanding 0.670s 75.425us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.720s 72.635us 1 1 100.00
rv_timer_tl_intg_err 0.970s 380.604us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.970s 380.604us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.490s 169.920us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.560s 46.876us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 14.110s 2584.662us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 108951438962178458416106878957138710571908366493431720106273590940917249152205 75
UVM_INFO @ 169920084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 82305843920844286251226339450198237691283835649501376739334677578445623548790 75
UVM_INFO @ 167146838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 67272189541686025161007541384242409789539525002287752472969672669288800655749 75
UVM_INFO @ 46875992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---