Simulation Results: sram_ctrl/main

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.22 %
  • code
  • 95.69 %
  • assert
  • 97.96 %
  • func
  • 95.00 %
  • block
  • 96.03 %
  • line
  • 96.75 %
  • branch
  • 94.17 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 5761.989us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 23.886us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.341us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 106.711us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 24.775us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 724.135us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 11.341us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 24.775us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 290.000s 317610.682us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 51.000s 12495.157us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 27.000s 5415.374us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 187.000s 24314.262us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 117.000s 4500.170us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 5.000s 1003.461us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 21.000s 7950.565us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 33.000s 9580.899us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 740.841us 1 1 100.00
sram_ctrl_partial_access_b2b 189.000s 14656.631us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 2886.902us 0 1 0.00
sram_ctrl_throughput_w_partial_write 3.000s 1322.975us 0 1 0.00
sram_ctrl_throughput_w_readback 5.000s 672.018us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 1049.845us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 1409.169us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 58.000s 14355.795us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 14.332us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 23.628us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 23.628us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 23.886us 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.341us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 24.775us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 41.617us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 23.886us 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.341us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 24.775us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 41.617us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 23.000s 30629.970us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 855.760us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 312.966us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 855.760us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 312.966us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 1049.845us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 1049.845us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.341us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 33.000s 9580.899us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 33.000s 9580.899us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 33.000s 9580.899us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 21.000s 7950.565us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 6.000s 847.659us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 23.000s 30629.970us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 695.143us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 5761.989us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 5761.989us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 33.000s 9580.899us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 855.760us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 21.000s 7950.565us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 855.760us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 855.760us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 5761.989us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 855.760us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 47.000s 2208.099us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 104401408220387965809367274374712352101652374709314410144757173947293321499227 86
UVM_INFO @ 2886901926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 44588816064883207109339840127735718096703692329944603063888870492927832766822 86
UVM_INFO @ 1322974531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 66201540778038512828917513744519794254888732664235696097606564394977030962246 86
UVM_INFO @ 672018198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---