Simulation Results: sram_ctrl/ret

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.15 %
  • code
  • 82.32 %
  • assert
  • 97.53 %
  • func
  • 90.60 %
  • block
  • 93.76 %
  • line
  • 94.99 %
  • branch
  • 89.36 %
  • toggle
  • 78.27 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 280.299us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 13.884us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.959us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 190.058us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 62.245us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 84.758us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 20.959us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 62.245us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 6.000s 540.880us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 123.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 6.000s 1026.001us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 189.000s 15551.565us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 350.462us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 19.000s 1048.177us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 618.575us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 9.000s 1193.792us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 62.524us 1 1 100.00
sram_ctrl_partial_access_b2b 115.000s 19454.030us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 1.000s 22.737us 0 1 0.00
sram_ctrl_throughput_w_partial_write 1.000s 25.530us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 109.371us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 3.000s 341.231us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 67.149us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 11.000s 5897.097us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 47.790us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 94.415us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 94.415us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 13.884us 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.959us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 62.245us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 19.493us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 13.884us 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.959us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 62.245us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 19.493us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 1597.592us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1592.075us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 1647.860us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1592.075us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 1647.860us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 341.231us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 341.231us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.959us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1193.792us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1193.792us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1193.792us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 618.575us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 187.409us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 1597.592us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 155.783us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 280.299us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 280.299us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 9.000s 1193.792us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1592.075us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 618.575us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1592.075us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1592.075us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 280.299us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1592.075us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 10.000s 326.316us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 54420550169916044499154253247543162234234343317747018545438110836917208092094 86
UVM_INFO @ 22737301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 5246298923685841501318335161658122228647479775567930930102195353232468993525 86
UVM_INFO @ 25530477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 25444880228414627918273708550352476713358641907252809270114897500285763004448 86
UVM_INFO @ 109370668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---