Simulation Results: sysrst_ctrl

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.22 %
  • code
  • 93.65 %
  • assert
  • 95.79 %
  • func
  • 63.21 %
  • line
  • 97.86 %
  • branch
  • 97.74 %
  • cond
  • 95.33 %
  • toggle
  • 99.77 %
  • FSM
  • 77.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 2.350s 2140.620us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.680s 2490.832us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 4.050s 2208.809us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.600s 2564.118us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 11.210s 6016.383us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 3.960s 2061.221us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 24.740s 70285.210us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 4.830s 2194.559us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.840s 2159.409us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 3.960s 2061.221us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.830s 2194.559us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 38.770s 84849.924us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 41.080s 92786.548us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 61.330s 75550.310us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 2.210s 3861.268us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.780s 2537.008us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.180s 2087.602us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 4.690s 2482.550us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.620s 2633.604us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 5.970s 7359.370us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 62.990s 40306.269us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 16.940s 10657.407us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.210s 2073.963us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.290s 2013.874us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.100s 2086.145us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.100s 2086.145us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 11.210s 6016.383us 1 1 100.00
sysrst_ctrl_csr_rw 3.960s 2061.221us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.830s 2194.559us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.660s 5087.349us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 11.210s 6016.383us 1 1 100.00
sysrst_ctrl_csr_rw 3.960s 2061.221us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.830s 2194.559us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.660s 5087.349us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 67.070s 42013.716us 1 1 100.00
sysrst_ctrl_tl_intg_err 72.050s 42381.236us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 72.050s 42381.236us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 7.660s 7125.238us 1 1 100.00