Simulation Results: uart

 
01/07/2026 15:30:33 DVSim: v1.49.12 sha: e600a7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.05 %
  • code
  • 91.61 %
  • assert
  • 98.56 %
  • func
  • 52.97 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.33 %
  • toggle
  • 74.49 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.850s 696.051us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.710s 52.051us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.660s 17.306us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.990s 319.456us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.960s 29.304us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.650s 28.431us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.660s 17.306us 1 1 100.00
uart_csr_aliasing 0.960s 29.304us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 9.940s 90276.114us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.850s 696.051us 1 1 100.00
uart_tx_rx 9.940s 90276.114us 1 1 100.00
parity_error 2 2 100.00
uart_intr 13.620s 16083.040us 1 1 100.00
uart_rx_parity_err 16.860s 69994.006us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 9.940s 90276.114us 1 1 100.00
uart_intr 13.620s 16083.040us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 28.540s 110237.144us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 10.570s 20192.529us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 8.930s 84847.175us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 13.620s 16083.040us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 13.620s 16083.040us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 13.620s 16083.040us 1 1 100.00
perf 1 1 100.00
uart_perf 231.020s 8750.310us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.180s 4042.117us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.180s 4042.117us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 14.820s 16690.161us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.230s 4965.608us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 5.320s 8914.611us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 23.310s 5330.012us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 197.680s 132121.136us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 32.600s 88741.229us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.670s 20.561us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.680s 54.148us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.070s 64.669us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.070s 64.669us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.710s 52.051us 1 1 100.00
uart_csr_rw 0.660s 17.306us 1 1 100.00
uart_csr_aliasing 0.960s 29.304us 1 1 100.00
uart_same_csr_outstanding 0.670s 25.535us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.710s 52.051us 1 1 100.00
uart_csr_rw 0.660s 17.306us 1 1 100.00
uart_csr_aliasing 0.960s 29.304us 1 1 100.00
uart_same_csr_outstanding 0.670s 25.535us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.740s 163.238us 1 1 100.00
uart_tl_intg_err 1.040s 105.993us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.040s 105.993us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 13.080s 1498.022us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 101776177782140126477264403648229650597951105845904075991107065261573190202532 75
UVM_ERROR @ 16234479869 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 16234500703 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (124 [0x7c] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 16234521537 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 16234542371 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (124 [0x7c] vs 255 [0xff]) reg name: uart_reg_block.rdata