Simulation Results: adc_ctrl

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.32 %
  • code
  • 91.14 %
  • assert
  • 92.06 %
  • func
  • 12.77 %
  • line
  • 98.06 %
  • branch
  • 96.35 %
  • cond
  • 85.73 %
  • toggle
  • 97.16 %
  • FSM
  • 78.38 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 2.640s 5883.864us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.710s 858.000us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.870s 485.635us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 11.640s 26419.661us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.440s 592.188us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.370s 541.355us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.870s 485.635us 1 1 100.00
adc_ctrl_csr_aliasing 1.440s 592.188us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.870s 490.197us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.720s 483.327us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.770s 399.043us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.780s 415.582us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 1.110s 436.877us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.760s 319.055us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.890s 291.479us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.020s 346.200us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 1.740s 3581.238us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 47.870s 47247.189us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 61.890s 90310.841us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 0.840s 616.368us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.960s 282.321us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.730s 500.597us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.250s 1478.624us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.250s 1478.624us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.710s 858.000us 1 1 100.00
adc_ctrl_csr_rw 0.870s 485.635us 1 1 100.00
adc_ctrl_csr_aliasing 1.440s 592.188us 1 1 100.00
adc_ctrl_same_csr_outstanding 6.160s 4155.592us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.710s 858.000us 1 1 100.00
adc_ctrl_csr_rw 0.870s 485.635us 1 1 100.00
adc_ctrl_csr_aliasing 1.440s 592.188us 1 1 100.00
adc_ctrl_same_csr_outstanding 6.160s 4155.592us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 4.190s 4493.074us 1 1 100.00
adc_ctrl_tl_intg_err 2.460s 4218.357us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 2.460s 4218.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 0.780s 852.328us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 12887639865763197410099345470115539980056424446325972333805851424486721561871 386
UVM_INFO @ 490196895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 20392288143811647906828377597109680441201476650990640813578673443344431987599 386
UVM_INFO @ 483326548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 93703493162329042592360272162251866912746062107004131393202079989599748648986 386
UVM_INFO @ 399042537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 113590382482438303876664244684961464599354044329292964506213805014298216514593 386
UVM_INFO @ 415581606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 15183291887966132665971697960011688260518702290608042023714190040649324211353 386
UVM_INFO @ 436877092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 68743624296541943778084705212309889202645224166274133159339486435066461202856 386
UVM_INFO @ 319055280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 101276961816488818357250100454825368340307243908224337507861113324128881678494 386
UVM_INFO @ 346200074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 26306216121227704866488323860307192549571994172563819351267373676427980375356 386
UVM_INFO @ 291479289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 58653935720852222808239299754612939175384216676849938810892576292688049076242 392
UVM_INFO @ 852327670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 105264933906674200602157089201297997993631730209878547099358534425413396845205 387
UVM_INFO @ 616368012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---